Alternatives and similar repositories for lorina:

Users that are interested in lorina are comparing it to the libraries listed below

• lsils / percy
  C++ header-only exact synthesis library
  ☆17Updated 2 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆25Updated 2 years ago
• lsils / bill
  C++ header-only reasoning library
  ☆14Updated 9 months ago
• msoeken / kitty
  C++ truth table library
  ☆53Updated last year
• amahzoon / genmul
  ☆16Updated 4 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆18Updated 5 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆71Updated 4 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆106Updated 5 months ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆52Updated last year
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated 9 months ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆194Updated last year
• msoeken / cirkit
  A circuit toolkit
  ☆100Updated 5 years ago
• cornell-zhang / datuner
  DATuner Repository
  ☆18Updated 6 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆30Updated last year
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆15Updated 8 years ago
• lsils / mockturtle
  C++ logic network library
  ☆228Updated 6 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 9 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆22Updated 4 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆54Updated 5 months ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆25Updated 2 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated last year
• aolofsson / IDEA
  ☆34Updated 5 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆29Updated 9 months ago
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆13Updated last year
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆76Updated 9 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 5 months ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• aolofsson / POSH
  ☆43Updated 5 years ago
• lana555 / dynamatic
  ☆86Updated last year