Alternatives and similar repositories for lorina:

Users that are interested in lorina are comparing it to the libraries listed below

• lsils / percy
  C++ header-only exact synthesis library
  ☆16Updated 2 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆25Updated 2 years ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• msoeken / kitty
  C++ truth table library
  ☆52Updated last year
• lsils / bill
  C++ header-only reasoning library
  ☆13Updated 8 months ago
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆14Updated 8 years ago
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆12Updated last year
• lsils / mockturtle
  C++ logic network library
  ☆225Updated 5 months ago
• cornell-zhang / datuner
  DATuner Repository
  ☆18Updated 6 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆64Updated 4 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆18Updated 5 months ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆30Updated last year
• SPbSAT / cirbo
  ☆17Updated last week
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆24Updated 2 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆28Updated 8 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆104Updated 4 months ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆193Updated 11 months ago
• wincle626 / HLS_Legup
  ☆26Updated 7 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆52Updated 4 months ago
• msoeken / cirkit
  A circuit toolkit
  ☆100Updated 5 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆22Updated 2 months ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆69Updated 3 weeks ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆51Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated last week
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆30Updated 4 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆101Updated last year
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆56Updated 8 months ago