Alternatives and similar repositories for kitty

Users that are interested in kitty are comparing it to the libraries listed below

• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆27Updated 2 years ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆37Updated last year
• msoeken / cirkit
  A circuit toolkit
  ☆103Updated 5 years ago
• lsils / mockturtle
  C++ logic network library
  ☆243Updated this week
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆194Updated last year
• lsils / bill
  C++ header-only reasoning library
  ☆17Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆18Updated 2 years ago
• Gy-Hu / E-Syn2
  E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)
  ☆19Updated last month
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆23Updated 3 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆85Updated 2 months ago
• nbulsi / also
  A logic synthesis tool
  ☆77Updated 3 weeks ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆33Updated last year
• gmeuli / caterpillar
  ☆26Updated 4 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated last month
• Gigantua / Espresso
  Espresso heuristic logic minimizer made C++20 Windows 10 compatible - University of California, Berkeley
  ☆54Updated last year
• muhos / ParaFROST
  A Parallel SAT Solver with GPU Accelerated Inprocessing
  ☆122Updated last month
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆81Updated this week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆110Updated 2 months ago
• rdaly525 / coreir
  ☆103Updated 3 years ago
• cuddorg / cudd
  CUDD Decision Diagram Package
  ☆139Updated last week
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated 2 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆95Updated this week
• classabbyamp / espresso-logic
  A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
  ☆153Updated 5 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆78Updated last year
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆227Updated this week
• shaowei-cai-group / X-SAT
  An advanced circuit-based sat solver
  ☆27Updated 5 months ago
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆49Updated 3 weeks ago