Alternatives and similar repositories for kitty

Users that are interested in kitty are comparing it to the libraries listed below

• msoeken / cirkit
  A circuit toolkit
  ☆105Updated 5 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆29Updated 2 years ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆37Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• lsils / mockturtle
  C++ logic network library
  ☆258Updated last month
• lsils / bill
  C++ header-only reasoning library
  ☆17Updated last year
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆198Updated last year
• lsils / percy
  C++ header-only exact synthesis library
  ☆18Updated 2 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆36Updated last year
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆15Updated 3 years ago
• classabbyamp / espresso-logic
  A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
  ☆163Updated 5 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆88Updated 2 months ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated 3 years ago
• nbulsi / also
  A logic synthesis tool
  ☆82Updated last month
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆90Updated last week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 5 months ago
• Gy-Hu / E-Syn2
  E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)
  ☆22Updated 4 months ago
• shaowei-cai-group / X-SAT
  An advanced circuit-based sat solver
  ☆35Updated 8 months ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆79Updated last year
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 3 months ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• amahzoon / genmul
  ☆18Updated 4 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆43Updated last month
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆226Updated this week
• rdaly525 / coreir
  ☆104Updated 3 years ago
• gmeuli / caterpillar
  ☆28Updated 4 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 6 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated 2 weeks ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆51Updated 3 weeks ago