lsils / kittyLinks
C++ truth table library
☆64Updated 6 months ago
Alternatives and similar repositories for kitty
Users that are interested in kitty are comparing it to the libraries listed below
Sorting:
- An advanced header-only exact synthesis library☆31Updated 3 years ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆38Updated last year
- A circuit toolkit☆107Updated 5 years ago
- C++ logic network library☆275Updated 4 months ago
- C++ header-only exact synthesis library☆17Updated 3 years ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- Showcase examples for EPFL logic synthesis libraries☆202Updated last year
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- Python library that provides methods for Boolean circuit manipulation, analysis, and synthesis☆32Updated last week
- C++ header-only reasoning library☆16Updated last year
- Integer Multiplier Generator for Verilog☆23Updated 7 months ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Updated 3 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆101Updated this week
- BTOR2 MLIR project☆26Updated 2 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- A generic parser and tool package for the BTOR2 format.☆46Updated 4 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Updated last year
- Testing processors with Random Instruction Generation☆52Updated 3 weeks ago
- An advanced circuit-based sat solver☆36Updated 11 months ago
- ELVE : ELVE Logic Visualization Engine☆11Updated 8 years ago
- FPGA synthesis tool powered by program synthesis☆54Updated last month
- A logic synthesis tool☆84Updated 4 months ago
- A Modeling and Verification Platform for SoCs using ILAs☆81Updated last year
- AIGER And-Inverter-Graph Library☆97Updated last month
- A tool for synthesizing Verilog programs☆109Updated 5 months ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆119Updated 8 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated 2 weeks ago
- ☆19Updated 5 years ago
- Debuggable hardware generator☆71Updated 2 years ago
- An open-source custom cache generator.☆34Updated last year