Alternatives and similar repositories for AxLS

Users that are interested in AxLS are comparing it to the libraries listed below

• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆58Updated 11 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆74Updated last week
• lnis-uofu / LSOracle
  IDEA project source files
  ☆110Updated last month
• parallaxsw / OpenSTA
  ☆95Updated this week
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆103Updated 5 months ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆52Updated last year
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆79Updated 4 years ago
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆66Updated 7 months ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆40Updated 6 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 5 years ago
• pkuzjx / eda-collection
  ☆107Updated 6 years ago
• zshi0616 / python-deepgate
  ☆26Updated last year
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆39Updated 5 months ago
• Ravenslofty / librecell
  ☆26Updated 4 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆131Updated 3 weeks ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆88Updated 7 months ago
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆85Updated last year
• bluesceada / iscas89_hl_verilog
  Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
  ☆15Updated 4 years ago
• NVlabs / INSTA
  ☆89Updated 5 months ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆81Updated 4 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆171Updated 3 months ago
• ABKGroup / PROBE3.0
  ☆49Updated last year
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated 3 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 5 months ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆44Updated last year
• The-OpenROAD-Project / asap7
  ☆216Updated 9 months ago
• Rishikesh973 / DTMF-Receiver-Logic-Synthesis-and-Physical-Design-
  DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node
  ☆12Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆29Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆63Updated 2 years ago