Alternatives and similar repositories for OPDB

Users that are interested in OPDB are comparing it to the libraries listed below

• lnis-uofu / LSOracle
  IDEA project source files
  ☆110Updated 2 months ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• pkuzjx / eda-collection
  ☆107Updated 6 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated last year
• aolofsson / IDEA
  ☆33Updated 5 years ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated 3 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆38Updated 2 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆64Updated 2 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆126Updated 2 years ago
• intel / aib-phy-hardware
  ☆67Updated 2 years ago
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆65Updated 3 years ago
• pulp-platform / svase
  ☆33Updated 11 months ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆17Updated 7 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆90Updated 5 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆181Updated this week
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated this week
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆74Updated 2 weeks ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 6 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆184Updated last year
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 5 years ago
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆133Updated 6 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆34Updated 6 months ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• chipsalliance / uvm-verilator
  ☆110Updated last month
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆116Updated last year