Alternatives and similar repositories for OPDB

Users that are interested in OPDB are comparing it to the libraries listed below

• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated 3 weeks ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated 9 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆113Updated this week
• intel / aib-phy-hardware
  ☆67Updated 2 years ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆47Updated 2 years ago
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆122Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆60Updated last year
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆65Updated 2 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆97Updated 3 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆50Updated 5 years ago
• lana555 / dynamatic
  ☆87Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated last month
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆78Updated 4 years ago
• pulp-platform / svase
  ☆32Updated 7 months ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆174Updated last year
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 3 months ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆84Updated 10 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆88Updated last year
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆127Updated 2 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆43Updated last year