Alternatives and similar repositories for datc_robust_design_flow

Users that are interested in datc_robust_design_flow are comparing it to the libraries listed below

• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆31Updated 5 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆55Updated 4 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆73Updated 7 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆30Updated 5 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆87Updated 4 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆57Updated last year
• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆21Updated 6 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated 3 weeks ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 10 months ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆47Updated 2 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆13Updated 7 years ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆52Updated 10 months ago
• ABKGroup / TritonRoute-WXL
  ☆30Updated 4 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆28Updated 3 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆29Updated last year
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆126Updated 10 months ago
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆11Updated 8 years ago
• IntelLabs / FloorSet
  ☆72Updated 5 months ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆104Updated last year
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• ieee-ceda-datc / RDF-2020
  ☆13Updated 3 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆31Updated 2 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 4 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆48Updated 4 months ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆122Updated last week