GJigar / ZYNQ_CNNLinks
☆19Updated 3 years ago
Alternatives and similar repositories for ZYNQ_CNN
Users that are interested in ZYNQ_CNN are comparing it to the libraries listed below
Sorting:
- Open IP in Hardware Description Language.☆29Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆31Updated last year
- ☆11Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆39Updated 8 years ago
- ☆40Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- ☆20Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20Updated 8 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- A verilog implementation for Network-on-Chip☆81Updated 7 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- Implement a bitonic sorting network on FPGA☆48Updated 4 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- ☆36Updated 2 years ago
- AHB DMA 32 / 64 bits☆58Updated 11 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆36Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆41Updated 3 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆21Updated 7 months ago
- AXI总线连接器☆105Updated 5 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- AHB Bus lite v3.0☆17Updated 6 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated last year