☆19Sep 12, 2022Updated 3 years ago
Alternatives and similar repositories for ZYNQ_CNN
Users that are interested in ZYNQ_CNN are comparing it to the libraries listed below
Sorting:
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- zero-riscy CPU Core☆17Jun 10, 2018Updated 7 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Mar 15, 2020Updated 5 years ago
- ☆22Feb 22, 2020Updated 6 years ago
- Codes to implement MobileNet V2 in a FPGA☆28Dec 21, 2020Updated 5 years ago
- CNN Implemetation on ZYNQ-7010☆25Sep 24, 2023Updated 2 years ago
- ☆24Mar 19, 2022Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆43Sep 26, 2023Updated 2 years ago
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.☆42Nov 17, 2014Updated 11 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- ☆10Oct 18, 2024Updated last year
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Time management library for embedded devices☆12Apr 21, 2019Updated 6 years ago
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆14Sep 5, 2023Updated 2 years ago
- mechatronics firmware☆13Apr 14, 2025Updated 10 months ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Design of High-Level Synthesis of Xilinx FFT IP core via FFT library☆13Jul 17, 2023Updated 2 years ago
- fpga i2c slave verilog hdl rtl☆16Nov 26, 2015Updated 10 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- Code repository for my articles on blogs.embarcadero.com and pythongui.org.☆13Feb 6, 2025Updated last year
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆12Mar 20, 2023Updated 2 years ago
- ☆14Jan 22, 2026Updated last month
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆21Jun 30, 2025Updated 8 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 9 years ago
- 电子科技大学硕士毕设☆10Jun 4, 2019Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 9 years ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- Exercism exercises in Tcl.☆11Feb 22, 2026Updated last week
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆16Nov 18, 2025Updated 3 months ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago