GJigar / ZYNQ_CNNLinks
☆19Updated 3 years ago
Alternatives and similar repositories for ZYNQ_CNN
Users that are interested in ZYNQ_CNN are comparing it to the libraries listed below
Sorting:
- Open IP in Hardware Description Language.☆28Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- upgrade to e203 (a risc-v core)☆45Updated 5 years ago
- ☆20Updated 3 years ago
- 大三上做的本科毕设,包含BNN 的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆20Updated 6 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- ☆11Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- ☆28Updated 6 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- An AXI DDR3 SDRAM controller for FPGA☆43Updated 2 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- ☆40Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Updated 11 years ago
- AXI总线连接器☆105Updated 5 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆34Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated last year
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Updated 5 years ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- ☆46Updated 4 years ago
- ☆57Updated 6 years ago
- AI Chip project☆34Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆61Updated 3 years ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni …☆26Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 3 years ago