Junyi-Liu / benchmarks-HLS
Benchmarks, testbenches, and transformed codes for high-level synthesis research
☆13Updated 7 years ago
Alternatives and similar repositories for benchmarks-HLS:
Users that are interested in benchmarks-HLS are comparing it to the libraries listed below
- Benchmarks for High-Level Synthesis☆10Updated 2 years ago
- ☆27Updated 7 years ago
- DASS HLS Compiler☆29Updated last year
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 8 months ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated this week
- DATuner Repository☆18Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆17Updated 7 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated 2 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- ☆24Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Updated 6 years ago
- ☆29Updated 6 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆34Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆23Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- ☆12Updated 2 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆25Updated 2 years ago
- Fast Floating Point Operators for High Level Synthesis☆20Updated 2 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆12Updated 4 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆12Updated 3 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago