asadalam / FINN_MatrixVector_RTLLinks
Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.github.io/FINN_MatrixVector_RTL/
☆16Updated 3 years ago
Alternatives and similar repositories for FINN_MatrixVector_RTL
Users that are interested in FINN_MatrixVector_RTL are comparing it to the libraries listed below
Sorting:
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆58Updated 5 years ago
- ☆23Updated 2 years ago
- ☆60Updated last month
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- ☆35Updated 3 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆46Updated 8 months ago
- ☆94Updated last year
- ☆71Updated 2 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 7 months ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- CNN accelerator☆27Updated 8 years ago
- ☆4Updated 4 years ago
- ☆33Updated 6 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- ☆29Updated 6 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 4 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆17Updated last month
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆37Updated 3 weeks ago
- ☆35Updated 4 years ago