asadalam / FINN_MatrixVector_RTL
Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.github.io/FINN_MatrixVector_RTL/
☆15Updated 3 years ago
Alternatives and similar repositories for FINN_MatrixVector_RTL:
Users that are interested in FINN_MatrixVector_RTL are comparing it to the libraries listed below
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆34Updated last week
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆20Updated last year
- ☆57Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆39Updated 6 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆23Updated 2 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- CNN accelerator☆28Updated 7 years ago
- ☆33Updated 6 years ago
- ☆71Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆43Updated last month
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated last year
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 5 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆74Updated 3 years ago
- ☆26Updated 5 years ago
- ☆29Updated 5 years ago
- An LSTM template and a few examples using Vivado HLS☆44Updated 11 months ago
- ☆3Updated 3 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated 10 months ago