Alternatives and similar repositories for FINN_MatrixVector_RTL

Users that are interested in FINN_MatrixVector_RTL are comparing it to the libraries listed below

• awai54st / LUTNet
  ☆63Updated 5 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆30Updated last year
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆101Updated last year
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 4 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 8 years ago
• MartaAndronic / NeuraLUT
  NeuraLUT-Assemble
  ☆43Updated 3 months ago
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆46Updated last year
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆97Updated last week
• awai54st / Logic-Shrinkage
  ☆22Updated 3 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆66Updated 3 weeks ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆34Updated 2 years ago
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆22Updated last year
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆26Updated 2 weeks ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆46Updated last year
• VeriGOOD-ML / public
  ☆64Updated 7 months ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆54Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆71Updated 6 years ago
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆146Updated 5 years ago
• gem5-X / TiC-SAT
  ☆19Updated 6 months ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆27Updated 4 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 8 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆31Updated 2 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆37Updated 5 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆49Updated 9 months ago
• hyoukjun / microswitch-noc
  ☆28Updated 6 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆82Updated 4 years ago