valar1234 / SDAILinks
An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool
☆15Updated 8 years ago
Alternatives and similar repositories for SDAI
Users that are interested in SDAI are comparing it to the libraries listed below
Sorting:
- HLS implemented systolic array structure☆41Updated 7 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.☆17Updated 6 years ago
- ☆72Updated 2 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago
- ☆71Updated 5 years ago
- ☆35Updated 6 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Updated 4 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- ☆70Updated 6 years ago
- ☆60Updated 5 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- PYNQ demo as seen at FPL 2018☆22Updated 4 years ago
- CNN accelerator☆27Updated 8 years ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 5 years ago
- ☆24Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated last week
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆24Updated 6 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- MAESTRO binary release☆22Updated 5 years ago
- ☆44Updated last year