valar1234 / SDAILinks
An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool
☆15Updated 8 years ago
Alternatives and similar repositories for SDAI
Users that are interested in SDAI are comparing it to the libraries listed below
Sorting:
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33Updated 6 years ago
- ☆72Updated 2 years ago
- ☆71Updated 5 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- ☆71Updated 6 years ago
- Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.☆17Updated 6 years ago
- ☆35Updated 6 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 7 years ago
- Residual Binarized Neural Network☆43Updated 7 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- An LSTM template and a few examples using Vivado HLS☆46Updated last year
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆70Updated 5 years ago
- ☆63Updated 5 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆17Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆66Updated 3 weeks ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago