ptoupas / amd-open-hardware-23Links
This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model architecture.
☆42Updated last year
Alternatives and similar repositories for amd-open-hardware-23
Users that are interested in amd-open-hardware-23 are comparing it to the libraries listed below
Sorting:
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 6 months ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆55Updated 5 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆45Updated 4 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 8 months ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- ☆30Updated 6 months ago
- AMD University Program HLS tutorial☆95Updated 7 months ago
- ☆46Updated 7 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- ☆65Updated 6 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆56Updated 4 months ago
- CNN accelerator implemented with Spinal HDL☆149Updated last year
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆82Updated 3 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆125Updated 3 months ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆38Updated 10 months ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆51Updated 7 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- PYNQ Composabe Overlays☆72Updated 11 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- ☆26Updated 2 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 4 months ago
- ☆14Updated 2 years ago
- Zynq-7000 DPU TRD☆45Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago