da-steve101 / twn_generatorLinks
Generate an FPGA design for a TWN
☆10Updated 5 years ago
Alternatives and similar repositories for twn_generator
Users that are interested in twn_generator are comparing it to the libraries listed below
Sorting:
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated last year
- ☆19Updated 4 years ago
- ☆60Updated 5 years ago
- An implementation of a BinaryConnect network for cifar10☆11Updated 5 years ago
- ☆23Updated 2 years ago
- ☆34Updated 6 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆141Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆14Updated 8 months ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆53Updated last year
- ☆72Updated 2 years ago
- ☆14Updated 5 years ago
- ☆71Updated 5 years ago
- ☆20Updated 6 months ago
- NeuraLUT-Assemble☆41Updated 2 weeks ago
- Classify modulation of signals☆15Updated 5 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆30Updated 10 months ago
- Quantized Training for Convolutional Neural Networks using Xilinx Brevitas☆12Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- ☆31Updated 10 months ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆20Updated 5 years ago
- Residual Binarized Neural Network☆43Updated 7 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- ☆20Updated 3 years ago
- ☆28Updated 5 months ago
- Open Source Compiler Framework using ONNX as Frontend and IR☆33Updated 3 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year