da-steve101 / twn_generator
Generate an FPGA design for a TWN
☆10Updated 5 years ago
Alternatives and similar repositories for twn_generator:
Users that are interested in twn_generator are comparing it to the libraries listed below
- Classify modulation of signals☆15Updated 5 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆20Updated last year
- ☆57Updated 4 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- An implementation of a BinaryConnect network for cifar10☆11Updated 5 years ago
- ☆19Updated 4 years ago
- ☆23Updated 2 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆29Updated 5 months ago
- ☆29Updated 5 years ago
- Open Source Compiler Framework using ONNX as Frontend and IR☆29Updated 2 years ago
- ☆19Updated 2 months ago
- ☆71Updated 2 years ago
- ☆33Updated 6 years ago
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆13Updated 3 months ago
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆29Updated 3 weeks ago
- Models and examples built with hls4ml☆12Updated 5 years ago
- Residual Binarized Neural Network☆43Updated 7 years ago
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆12Updated 3 years ago
- CNN accelerator☆28Updated 7 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆15Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆137Updated 5 years ago
- ☆22Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆34Updated 4 years ago
- ☆14Updated 5 years ago
- ☆26Updated 3 weeks ago
- HLS implemented systolic array structure☆41Updated 7 years ago