embedeep / FREE-TPU-V3plus-for-FPGA
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
☆145Updated last year
Alternatives and similar repositories for FREE-TPU-V3plus-for-FPGA:
Users that are interested in FREE-TPU-V3plus-for-FPGA are comparing it to the libraries listed below
- IC implementation of TPU☆122Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆99Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆196Updated 2 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆149Updated 10 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆157Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆149Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆30Updated 2 years ago
- IC implementation of Systolic Array for TPU☆232Updated 6 months ago
- An AXI4 crossbar implementation in SystemVerilog☆145Updated this week
- ☆38Updated 4 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆150Updated 5 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆118Updated 2 months ago
- ☆108Updated 4 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆181Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆85Updated 6 years ago
- AXI DMA 32 / 64 bits☆112Updated 10 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆72Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆100Updated 3 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆95Updated 2 months ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆117Updated 2 months ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- AXI总线连接器