embedeep / FREE-TPU-V3plus-for-FPGALinks
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
☆152Updated 2 years ago
Alternatives and similar repositories for FREE-TPU-V3plus-for-FPGA
Users that are interested in FREE-TPU-V3plus-for-FPGA are comparing it to the libraries listed below
Sorting:
- IC implementation of Systolic Array for TPU☆263Updated 9 months ago
- IC implementation of TPU☆128Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆220Updated 2 years ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆135Updated 5 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆123Updated 5 months ago
- Small-scale Tensor Processing Unit built on an FPGA☆194Updated 6 years ago
- ☆65Updated 6 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆156Updated 6 years ago
- DPU on PYNQ☆225Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆156Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- ☆43Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆164Updated last month
- AMD University Program HLS tutorial☆99Updated 9 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆34Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- ☆200Updated last year
- ☆113Updated 5 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆58Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆93Updated 2 weeks ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆87Updated 2 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆128Updated 2 months ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆350Updated last year
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆46Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆88Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago