FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
☆179Jun 9, 2023Updated 3 years ago
Alternatives and similar repositories for FREE-TPU-V3plus-for-FPGA
Users that are interested in FREE-TPU-V3plus-for-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆276May 6, 2023Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆177Jul 25, 2019Updated 7 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆579Jan 5, 2019Updated 7 years ago
- AI Chip project☆34Jul 14, 2021Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆163Feb 11, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆62Nov 22, 2023Updated 2 years ago
- IC implementation of TPU☆160Dec 18, 2019Updated 6 years ago
- An FPGA Accelerator for Transformer Inference☆97Apr 29, 2022Updated 4 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆230Aug 4, 2019Updated 7 years ago
- Research and Materials on Hardware implementation of Transformer Model☆313Feb 28, 2025Updated last year
- C++ code for HLS FPGA implementation of transformer☆25Sep 11, 2024Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆271Mar 24, 2024Updated 2 years ago
- ☆56Jan 14, 2021Updated 5 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆144May 10, 2024Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆781Dec 6, 2017Updated 8 years ago
- ☆15Aug 10, 2023Updated 3 years ago
- IC implementation of Systolic Array for TPU☆371Oct 21, 2024Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆39May 20, 2026Updated 4 months ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆38Aug 28, 2025Updated last year
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆20Aug 14, 2026Updated last month
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆392Updated this week
- ☆265Apr 8, 2024Updated 2 years ago
- ☆46Mar 31, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Mar 22, 2024Updated 2 years ago
- An FPGA design for simulating biological neurons☆19Jul 5, 2024Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆52Jul 1, 2020Updated 6 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆57Updated this week
- ☆43Apr 28, 2019Updated 7 years ago
- A Convolutional Neural Network Accelerator implementation on FPGA, xilinx (xczu7ev-ffvc1156-2-i), The inference of yolov8 took 60ms.☆579Jul 17, 2025Updated last year
- 4-Layer XC7Z010 DDR3 Layout☆19Nov 25, 2021Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module