FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
☆177Jun 9, 2023Updated 3 years ago
Alternatives and similar repositories for FREE-TPU-V3plus-for-FPGA
Users that are interested in FREE-TPU-V3plus-for-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆275May 6, 2023Updated 3 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆176Jul 25, 2019Updated 7 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆575Jan 5, 2019Updated 7 years ago
- AI Chip project☆34Jul 14, 2021Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆161Feb 11, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆62Nov 22, 2023Updated 2 years ago
- IC implementation of TPU☆160Dec 18, 2019Updated 6 years ago
- An FPGA Accelerator for Transformer Inference☆97Apr 29, 2022Updated 4 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆230Aug 4, 2019Updated 7 years ago
- Research and Materials on Hardware implementation of Transformer Model☆311Feb 28, 2025Updated last year
- C++ code for HLS FPGA implementation of transformer☆25Sep 11, 2024Updated last year
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆267Mar 24, 2024Updated 2 years ago
- ☆56Jan 14, 2021Updated 5 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆143May 10, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆778Dec 6, 2017Updated 8 years ago
- ☆15Aug 10, 2023Updated 3 years ago
- IC implementation of Systolic Array for TPU☆370Oct 21, 2024Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆39May 20, 2026Updated 3 months ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆38Aug 28, 2025Updated last year
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆19Aug 14, 2026Updated 3 weeks ago
- ☆265Apr 8, 2024Updated 2 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆392Dec 27, 2023Updated 2 years ago
- ☆46Mar 31, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆15Mar 22, 2024Updated 2 years ago
- An FPGA design for simulating biological neurons☆20Jul 5, 2024Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆52Jul 1, 2020Updated 6 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆56Updated this week
- ☆43Apr 28, 2019Updated 7 years ago
- A Convolutional Neural Network Accelerator implementation on FPGA, xilinx (xczu7ev-ffvc1156-2-i), The inference of yolov8 took 60ms.☆576Jul 17, 2025Updated last year
- 4-Layer XC7Z010 DDR3 Layout☆18Nov 25, 2021Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆175May 10, 2025Updated last year
- A novel FPGA-based intent recognition systemutilizing deep recurrent neural networks☆26Aug 25, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- An High-Performance SLAM Hardware Accelerator Implementation for FPGA☆74Nov 10, 2024Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆52Jun 24, 2022Updated 4 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆179Mar 5, 2025Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆38Mar 12, 2026Updated 5 months ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆70Dec 26, 2019Updated 6 years ago
- ☆19Nov 11, 2024Updated last year
- Berkeley's Spatial Array Generator☆1,447Updated this week