Alternatives and similar repositories for FREE-TPU-V3plus-for-FPGA

Users that are interested in FREE-TPU-V3plus-for-FPGA are comparing it to the libraries listed below

• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆154Updated last year
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆154Updated 7 months ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆135Updated 5 years ago
• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆205Updated 6 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆290Updated last year
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆230Updated 2 years ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆134Updated 8 months ago
• cea-wind / SimpleTPU
  A FPGA Based CNN accelerator, following Google's TPU V1.
  ☆161Updated 6 years ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆116Updated last year
• intel / fpga-npu
  ☆220Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆70Updated 6 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆201Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆105Updated 5 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆168Updated last year
• dldldlfma / super_small_toy_tpu
  ☆42Updated 4 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆173Updated 5 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆120Updated 5 years ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆228Updated 2 months ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆57Updated 3 years ago
• cathalmccabe / PYNQ_tutorials
  ☆97Updated last year
• maomran / softmax
  Verilog implementation of Softmax function
  ☆73Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆177Updated last month
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆82Updated 2 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆95Updated last week
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆208Updated 3 weeks ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆114Updated 3 months ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆98Updated 9 months ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆135Updated 5 months ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆36Updated 3 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆194Updated 7 years ago