RTL code for the DPU chip designed for irregular graphs
☆14May 30, 2022Updated 4 years ago
Alternatives and similar repositories for DPU_DAG_Processing_Unit
Users that are interested in DPU_DAG_Processing_Unit are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A DAG processor and compiler for a tree-based spatial datapath.☆17Aug 24, 2022Updated 4 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆27Jul 12, 2023Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Feb 8, 2023Updated 3 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆18Oct 6, 2019Updated 7 years ago
- ☆11Mar 22, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- a Computing In Memory emULATOR framework☆16May 19, 2024Updated 2 years ago
- SHA-256 ASIC - full open-source signoff flow (RTL to GDSII) on SkyWater 130nm☆16Aug 14, 2026Updated 2 months ago
- This repository contains the artifacts for the MLSys 2026 paper AgenticCache.☆13Apr 22, 2026Updated 6 months ago
- Multi-port BRAM IP for ASIC and FPGA☆14Apr 21, 2021Updated 5 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Hardware acceleration for transformer attention mechanisms on NVIDIA Deep Learning Accelerator (NVDLA), enabling efficient inference of…☆20Mar 30, 2025Updated last year
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 3 years ago
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆15Sep 12, 2022Updated 4 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆22Oct 29, 2025Updated last year
- Starting from Attention, teaching the realization of VIT and other vision Transformer models hand in hand.☆12Nov 20, 2021Updated 4 years ago
- My blog — https://twilco.github.io☆13Apr 26, 2026Updated 6 months ago
- JDMR-Net: Joint Detection and Modulation Recognition Networks for LPI Radar Signals☆16May 24, 2023Updated 3 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Nov 27, 2025Updated 11 months ago
- awesome image and video denoising, state of the art networks☆10Aug 2, 2019Updated 7 years ago
- Binary Neural Networks research project☆11Aug 21, 2021Updated 5 years ago
- FPGA implementation of a simple scanline based 2d graphics engine☆25Feb 26, 2019Updated 7 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆36Aug 1, 2020Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Backpropagation Neural Network for Multivariate Time Series Forecasting (multi input single output: 2 inputs and 1 output)☆23Apr 1, 2021Updated 5 years ago
- ☆13Oct 2, 2025Updated last year
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 6 years ago
- LVGL DEMOS STM32☆10Nov 15, 2022Updated 3 years ago
- This is a robot simulation project based on Webots and C++ @ June 2020☆13Jun 24, 2020Updated 6 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆15Aug 28, 2025Updated last year
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 10 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆36Mar 21, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆15Jun 1, 2025Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Jul 14, 2020Updated 6 years ago
- ☆12Jan 31, 2023Updated 3 years ago
- Course Notes for CS61C☆19Oct 26, 2026Updated last week
- End to end framework to replace camera ISP with a deep learning model.☆16Jan 16, 2021Updated 5 years ago
- double_fpu_verilog☆22Jul 17, 2014Updated 12 years ago