RTL code for the DPU chip designed for irregular graphs
☆14May 30, 2022Updated 3 years ago
Alternatives and similar repositories for DPU_DAG_Processing_Unit
Users that are interested in DPU_DAG_Processing_Unit are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A DAG processor and compiler for a tree-based spatial datapath.☆16Aug 24, 2022Updated 3 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆24Jul 12, 2023Updated 2 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆43Feb 8, 2023Updated 3 years ago
- an elegant, easy-to-use chinese latex resume template☆42Apr 16, 2026Updated 2 weeks ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Oct 6, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- [CVPRW 2025] Learned Lightweight Smartphone ISP with Unpaired Data (PyTorch)☆23Jun 20, 2025Updated 10 months ago
- Starting from Attention, teaching the realization of VIT and other vision Transformer models hand in hand.☆13Nov 20, 2021Updated 4 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 5 months ago
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆15Sep 12, 2022Updated 3 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆33Aug 1, 2020Updated 5 years ago
- JDMR-Net: Joint Detection and Modulation Recognition Networks for LPI Radar Signals☆16May 24, 2023Updated 2 years ago
- awesome image and video denoising, state of the art networks☆10Aug 2, 2019Updated 6 years ago
- Combination of Analog Circuit Sizing and DL.☆18Mar 24, 2023Updated 3 years ago
- SNN on FPGA☆13Apr 26, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 5 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Aug 28, 2025Updated 8 months ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆35Mar 21, 2020Updated 6 years ago
- Digital Design Lab Spring 2019 Final Project☆13Jun 17, 2019Updated 6 years ago
- End to end framework to replace camera ISP with a deep learning model.☆16Jan 16, 2021Updated 5 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- An Open-Source Processor for Accelerating Spiking Neural Network☆12Sep 30, 2022Updated 3 years ago
- LVGL DEMOS STM32☆10Nov 15, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆15Jun 1, 2025Updated 11 months ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- CPU implementation of the Image stitching using FAST. For FPGA implementation visit tharaka27-SocStitcher.☆12Jun 19, 2020Updated 5 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆41Jan 15, 2024Updated 2 years ago
- ☆62Feb 29, 2024Updated 2 years ago
- a Computing In Memory emULATOR framework☆15May 19, 2024Updated last year
- Backpropagation Neural Network for Multivariate Time Series Forecasting (multi input single output: 2 inputs and 1 output)☆23Apr 1, 2021Updated 5 years ago
- RDMA programming examples using Soft-RoCE☆13Aug 13, 2021Updated 4 years ago
- SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset i…☆26Nov 11, 2025Updated 5 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Implementation of One-step Latent-free Image Generation with Pixel Mean Flows (Lu et al., 2026)☆90Feb 2, 2026Updated 3 months ago
- bitfusion verilog implementation☆13Feb 21, 2022Updated 4 years ago
- This is the official employment of "ISPDiffuser: Learning RAW-to-sRGB Mappings with Texture-Aware Diffusion Models and Histogram-Guided C…☆31May 21, 2025Updated 11 months ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 6 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆17Sep 9, 2023Updated 2 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆78Mar 30, 2023Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆49Dec 3, 2023Updated 2 years ago