gju06051 / TPU_HW_VerilogLinks
☆14Updated 2 years ago
Alternatives and similar repositories for TPU_HW_Verilog
Users that are interested in TPU_HW_Verilog are comparing it to the libraries listed below
Sorting:
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆33Updated 6 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆11Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- AIChip 2021 project, NCKU☆18Updated 4 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆10Updated 5 years ago
- ☆20Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆44Updated 8 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year
- ☆27Updated 5 years ago
- SoC Based on ARM Cortex-M3☆32Updated 3 weeks ago
- ☆65Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated this week
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆38Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆32Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- HLS for Networks-on-Chip☆34Updated 4 years ago