gju06051 / TPU_HW_VerilogLinks
☆14Updated 2 years ago
Alternatives and similar repositories for TPU_HW_Verilog
Users that are interested in TPU_HW_Verilog are comparing it to the libraries listed below
Sorting:
- ☆40Updated 6 years ago
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 3 years ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated last month
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 5 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- ☆29Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆37Updated 3 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- ☆26Updated 4 years ago
- ☆31Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- SoC Based on ARM Cortex-M3☆36Updated 8 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- ☆20Updated 3 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆20Updated 9 months ago