gju06051 / TPU_HW_VerilogLinks
☆14Updated 2 years ago
Alternatives and similar repositories for TPU_HW_Verilog
Users that are interested in TPU_HW_Verilog are comparing it to the libraries listed below
Sorting:
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- ☆34Updated 6 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆10Updated 5 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆65Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- ☆29Updated 4 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- ☆65Updated 6 years ago
- ☆14Updated 2 years ago
- ☆10Updated 5 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- EE577b-Course-Project☆18Updated 5 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆25Updated 2 years ago
- ☆27Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- General Purpose AXI Direct Memory Access☆53Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- ☆56Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 4 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago