Alternatives and similar repositories for TiC-SAT:

Users that are interested in TiC-SAT are comparing it to the libraries listed below

• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆25Updated 9 months ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 3 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆76Updated 3 years ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆15Updated 9 months ago
• fffasttime / AnyPackingNet
  ☆26Updated last month
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆51Updated last week
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆49Updated last month
• ebby-s / MX-for-FPGA
  Implementation of Microscaling data formats in SystemVerilog.
  ☆17Updated 8 months ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆40Updated 7 months ago
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• KULeuven-MICAS / tinyvers
  TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.
  ☆17Updated last year
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆65Updated 2 months ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆40Updated last year
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆43Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆32Updated 6 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆18Updated 4 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆27Updated last year
• hngenc / stellar
  ☆27Updated 6 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆38Updated 2 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆51Updated last month
• wubinyi / Convolutional-Neural-Network-Accelerator
  Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).
  ☆21Updated 6 years ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆52Updated 3 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆39Updated 7 months ago