gem5-X / TiC-SATLinks
☆20Updated 8 months ago
Alternatives and similar repositories for TiC-SAT
Users that are interested in TiC-SAT are comparing it to the libraries listed below
Sorting:
- ☆38Updated 3 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 3 months ago
- eyeriss-chisel3☆40Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 6 months ago
- A systolic array matrix multiplier☆30Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆79Updated 2 months ago
- vector accelerating unit☆35Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 11 months ago
- ☆63Updated 9 months ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- ☆29Updated 6 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- Open-source of MSD framework☆16Updated 2 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆86Updated 5 months ago
- A list of our chiplet simulaters☆47Updated 7 months ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- 基于FP16的二维脉动阵列电路设计☆13Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆56Updated 2 years ago
- ☆72Updated 7 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆31Updated 5 months ago
- Verilog implementation of Softmax function☆78Updated 3 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆36Updated 3 years ago
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- ☆45Updated last week
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆36Updated 2 years ago