zjru / COMBALinks
A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications
☆38Updated 5 years ago
Alternatives and similar repositories for COMBA
Users that are interested in COMBA are comparing it to the libraries listed below
Sorting:
- DASS HLS Compiler☆29Updated 2 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Updated 5 years ago
- ☆24Updated 5 years ago
- ☆60Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 4 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Updated last month
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Systolic array implementations for Cholesky, LU, and QR decomposition☆47Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Updated 8 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆24Updated 4 years ago
- ☆10Updated 3 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- ☆30Updated 6 years ago
- CGRA Compilation Framework☆91Updated 2 years ago
- EQueue Dialect☆41Updated 3 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆72Updated 2 years ago
- ☆25Updated last year
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago