zjru / COMBALinks
A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications
☆38Updated 5 years ago
Alternatives and similar repositories for COMBA
Users that are interested in COMBA are comparing it to the libraries listed below
Sorting:
- Benchmarks for Accelerator Design and Customized Architectures☆131Updated 5 years ago
- ☆59Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆71Updated 7 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆24Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆30Updated 6 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆46Updated 11 months ago
- ☆103Updated last year
- CGRA Compilation Framework☆88Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- ☆87Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 4 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- HLS-based Graph Processing Framework on FPGAs☆151Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- ☆10Updated 2 years ago
- ☆25Updated last year
- A high-level performance analysis tool for FPGA-based accelerators☆20Updated 8 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆43Updated 8 years ago