zjru / COMBALinks
A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications
☆36Updated 4 years ago
Alternatives and similar repositories for COMBA
Users that are interested in COMBA are comparing it to the libraries listed below
Sorting:
- Benchmarks for Accelerator Design and Customized Architectures☆129Updated 5 years ago
- ☆24Updated 4 years ago
- ☆58Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- DASS HLS Compiler☆29Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆62Updated 3 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆60Updated 3 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated 2 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- CGRA Compilation Framework☆85Updated 2 years ago
- ☆86Updated last year
- ☆92Updated last year
- EQueue Dialect☆40Updated 3 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆43Updated 8 months ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆75Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- gem5 repository to study chiplet-based systems☆76Updated 6 years ago
- Dataset for ML-guided Accelerator Design☆37Updated 7 months ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- A Generic Distributed Auto-Tuning Infrastructure☆22Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- ☆16Updated 2 months ago