EPFL-LAP / dynamaticLinks
DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
☆141Updated this week
Alternatives and similar repositories for dynamatic
Users that are interested in dynamatic are comparing it to the libraries listed below
Sorting:
- high-performance RTL simulator☆180Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- Open-source RTL logic simulator with CUDA acceleration☆225Updated 3 weeks ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆108Updated 5 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 4 months ago
- ☆87Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 2 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆113Updated this week
- Vector Acceleration IP core for RISC-V*☆184Updated 5 months ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- Chisel RISC-V Vector 1.0 Implementation☆115Updated 3 weeks ago
- ☆61Updated this week
- A tool for synthesizing Verilog programs☆105Updated 2 months ago
- A hardware synthesis framework with multi-level paradigm☆41Updated 9 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆122Updated 2 weeks ago
- A dynamic verification library for Chisel.☆156Updated 11 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- A Chisel RTL generator for network-on-chip interconnects☆215Updated 2 months ago
- Next generation CGRA generator☆115Updated this week
- Unit tests generator for RVV 1.0☆92Updated last month
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆50Updated last year
- ☆63Updated 5 months ago
- A Fast, Low-Overhead On-chip Network☆231Updated last week
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- ☆47Updated 9 months ago
- ☆50Updated 3 months ago