Alternatives and similar repositories for dynamatic

Users that are interested in dynamatic are comparing it to the libraries listed below

• ucsc-vama / essent
  high-performance RTL simulator
  ☆185Updated last year
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆53Updated 2 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆126Updated 3 months ago
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆79Updated 2 weeks ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆252Updated 3 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆116Updated 2 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆135Updated this week
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆108Updated 4 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆42Updated last week
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆64Updated last year
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆121Updated this week
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆152Updated this week
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆55Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last month
• StanfordAHA / aha
  ☆62Updated last week
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆117Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆55Updated 5 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆99Updated 2 months ago
• lana555 / dynamatic
  ☆87Updated last year
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆43Updated last year
• tenstorrent / whisper
  ☆74Updated last week
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆81Updated 4 months ago
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆234Updated this week
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆118Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆176Updated 2 weeks ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆166Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago