ferrandi / PandA-bambu
PandA-bambu public repository
☆257Updated 2 months ago
Alternatives and similar repositories for PandA-bambu:
Users that are interested in PandA-bambu are comparing it to the libraries listed below
- Build Customized FPGA Implementations for Vivado☆308Updated this week
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆165Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆145Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆265Updated 4 months ago
- ☆86Updated last year
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆246Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆189Updated 2 weeks ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆119Updated 9 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆163Updated 4 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆169Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆268Updated 2 weeks ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- magma circuits☆259Updated 5 months ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆318Updated 2 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆412Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated this week
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆252Updated last week
- ☆103Updated 5 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆215Updated 2 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆166Updated 5 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆363Updated 2 weeks ago
- A scalable High-Level Synthesis framework on MLIR☆252Updated 10 months ago
- Network on Chip Implementation written in SytemVerilog☆171Updated 2 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆127Updated last year
- Vitis HLS LLVM source code and examples☆384Updated 5 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆213Updated last week
- ☆310Updated 6 months ago
- ☆41Updated 6 months ago
- A Fast, Low-Overhead On-chip Network☆184Updated this week
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year