cornell-zhang / hcl-dialect
HeteroCL-MLIR dialect for accelerator design
☆38Updated 3 months ago
Related projects: ⓘ
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆29Updated 4 months ago
- Polyhedral High-Level Synthesis in MLIR☆27Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆51Updated 2 weeks ago
- agile hardware-software co-design☆42Updated 2 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆22Updated 4 months ago
- A polyhedral compiler for hardware accelerators☆55Updated last month
- EQueue Dialect☆38Updated 2 years ago
- Bridging polyhedral analysis tools to the MLIR framework☆99Updated last year
- Data-Centric MLIR dialect☆37Updated 11 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆43Updated last year
- Code base for OOPSLA'24 paper: UniSparse: An Intermediate Language for General Sparse Format Customization☆28Updated 3 months ago
- A hardware synthesis framework with multi-level paradigm☆31Updated last year
- A graph linear algebra overlay☆47Updated last year
- ☆76Updated this week
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated last year
- CGRA framework with vectorization support.☆18Updated 5 months ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆17Updated last year
- ETHZ Heterogeneous Accelerated Compute Cluster.☆28Updated 3 weeks ago
- Example for running IREE in a bare-metal Arm environment.☆22Updated this week
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆45Updated 4 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆53Updated this week
- ☆22Updated 3 years ago
- ☆56Updated last year
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆57Updated 2 years ago
- ☆46Updated this week
- A stream to RTL compiler based on MLIR and CIRCT☆15Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆43Updated 2 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆62Updated 5 years ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆13Updated last year
- Floating point modules for CHISEL☆27Updated 9 years ago