breagen / MachSuiteLinks
Benchmarks for Accelerator Design and Customized Architectures
☆122Updated 5 years ago
Alternatives and similar repositories for MachSuite
Users that are interested in MachSuite are comparing it to the libraries listed below
Sorting:
- ☆86Updated last year
- CGRA Compilation Framework☆83Updated last year
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆129Updated last week
- ☆91Updated last year
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆165Updated last year
- ☆44Updated this week
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆170Updated this week
- An integrated CGRA design framework☆88Updated 2 months ago
- A pre-RTL, power-performance model for fixed-function accelerators☆176Updated last year
- gem5 repository to study chiplet-based systems☆74Updated 6 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆72Updated 3 weeks ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆237Updated 2 years ago
- CGRA framework with vectorization support.☆30Updated 3 weeks ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆152Updated 2 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- ☆58Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆91Updated 8 months ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆186Updated 4 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- gem5 Tips & Tricks☆70Updated 5 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- Fast and accurate DRAM power and energy estimation tool☆163Updated last week
- ☆53Updated 2 months ago