breagen / MachSuiteLinks
Benchmarks for Accelerator Design and Customized Architectures
☆129Updated 5 years ago
Alternatives and similar repositories for MachSuite
Users that are interested in MachSuite are comparing it to the libraries listed below
Sorting:
- CGRA Compilation Framework☆88Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- ☆97Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- A pre-RTL, power-performance model for fixed-function accelerators☆180Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- An integrated CGRA design framework☆91Updated 6 months ago
- ☆87Updated last year
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆197Updated 5 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 3 months ago
- gem5 repository to study chiplet-based systems☆81Updated 6 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆248Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆74Updated 3 weeks ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆113Updated 2 years ago
- ☆61Updated last week
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆125Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- ☆58Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆70Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆225Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A DSL for Systolic Arrays☆81Updated 6 years ago
- ☆49Updated 3 months ago
- ☆59Updated 6 months ago
- Fast and accurate DRAM power and energy estimation tool☆178Updated 2 weeks ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago