HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
☆16Sep 25, 2024Updated last year
Alternatives and similar repositories for HeteroGen
Users that are interested in HeteroGen are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Benchmarks for High-Level Synthesis☆11Mar 17, 2023Updated 3 years ago
- ☆12Jun 14, 2023Updated 3 years ago
- ☆18Mar 7, 2019Updated 7 years ago
- Mako is a low-pause, high-throughput garbage collector designed for memory-disaggregated datacenters.☆15Sep 2, 2024Updated last year
- ☆10Jan 15, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Dataset for ML-guided Accelerator Design☆45Nov 18, 2024Updated last year
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 3 years ago
- ☆10Sep 19, 2021Updated 4 years ago
- ☆63Aug 4, 2023Updated 3 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆14Aug 18, 2017Updated 8 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆17May 12, 2022Updated 4 years ago
- Implement CollAFL using LLVM LTO pass on afl++.☆12Sep 24, 2020Updated 5 years ago
- Dorylus: Affordable, Scalable, and Accurate GNN Training☆76May 31, 2021Updated 5 years ago
- APB Logic☆29Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆20Dec 3, 2019Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆173Nov 7, 2023Updated 2 years ago
- Bamboo is a system for running large pipeline-parallel DNNs affordably, reliably, and efficiently using spot instances.☆55Dec 11, 2022Updated 3 years ago
- HLSyn benchmark for paper "Towards a Comprehensive Benchmark for FPGA Targeted High-Level Synthesis"☆33Dec 13, 2023Updated 2 years ago
- MemLiner is a remote-memory-friendly runtime system.☆31Nov 1, 2022Updated 3 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA☆11Mar 13, 2026Updated 4 months ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆19Dec 12, 2025Updated 7 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆57Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆29Jun 18, 2020Updated 6 years ago
- ACM TODAES Best Paper Award, 2022☆35Oct 24, 2023Updated 2 years ago
- An open-source key-value SSD emulator built on top of FEMU. (ASPLOS '25)☆12Mar 31, 2025Updated last year
- VQPy: An object-oriented approach to modern video analytics☆42Oct 28, 2024Updated last year
- Accelerated Image Reconstruction using Generative Adversarial Networks on Cloud FPGAs☆11Aug 27, 2021Updated 4 years ago
- ☆12Aug 5, 2023Updated 3 years ago
- ☆20Aug 9, 2022Updated 4 years ago
- ☆12Sep 11, 2020Updated 5 years ago
- Official Implementation of PixelRNN: In-Pixel Recurrent Neural Networks for End-to-end--optimized Perception with Neural Sensors☆18Oct 27, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Circuit Simulator in C++/SFML☆12Feb 25, 2025Updated last year
- A pipeline to generate artificial rgb/depth image datasets using gazebo Simulator☆15Mar 9, 2022Updated 4 years ago
- ☆37Apr 10, 2026Updated 4 months ago
- Needle in the Repo (NITR) dataset for maintainability issues in AI generated repository edits☆32Aug 2, 2026Updated last week
- Hybrid BFS on Xilinx Zynq☆18Jun 9, 2015Updated 11 years ago
- FPGA Verilog HDL design project (DE1-SoC)☆13Jan 19, 2018Updated 8 years ago
- ☆15May 23, 2024Updated 2 years ago