UCLA-SEAL / HeteroGenLinks
HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
☆17Updated last year
Alternatives and similar repositories for HeteroGen
Users that are interested in HeteroGen are comparing it to the libraries listed below
Sorting:
- Heterogeneous simulator for DECADES Project☆32Updated last year
- ☆59Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆49Updated 3 years ago
- ☆29Updated 8 years ago
- Polyhedral High-Level Synthesis in MLIR☆34Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Updated 5 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- EQueue Dialect☆40Updated 3 years ago
- STONNE Simulator integrated into SST Simulator☆21Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- The Chronos FPGA Framework to accelerate ordered applications☆22Updated 5 years ago
- CGRA Compilation Framework☆88Updated 2 years ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆21Updated last year
- ILA Model Database☆24Updated 5 years ago
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆58Updated 6 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- ☆24Updated 4 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- Artifact, reproducibility, and testing utilites for gem5☆23Updated 4 years ago
- ☆24Updated 4 years ago
- A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.☆39Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year