Alternatives and similar repositories for polsca:

Users that are interested in polsca are comparing it to the libraries listed below

• cornell-zhang / hcl-dialect
  HeteroCL-MLIR dialect for accelerator design
  ☆41Updated 4 months ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆36Updated 2 weeks ago
• wincle626 / HLS_Legup
  ☆26Updated 7 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆48Updated last year
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 4 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 5 months ago
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 2 years ago
• IntelLabs / t2sp
  Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
  ☆30Updated 8 months ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆21Updated 2 weeks ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆55Updated 6 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆55Updated 3 months ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆27Updated last year
• icgrp / hipr
  ☆15Updated last year
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆21Updated this week
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆38Updated last month
• TeCSAR-UNCC / gem5-SALAM
  ☆89Updated 11 months ago
• UCLA-SEAL / HeteroGen
  HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
  ☆17Updated 4 months ago
• sfu-arch / muir
  ☆23Updated 4 years ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆38Updated last year
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• heterosys / mlir-vitis
  📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
  ☆13Updated 2 years ago
• pku-liang / ksim
  ☆38Updated 2 weeks ago
• PrincetonUniversity / MosaicSim
  Heterogeneous simulator for DECADES Project
  ☆31Updated 8 months ago
• SwarmArch / sim
  ordspecsim: The Swarm architecture simulator
  ☆24Updated last year
• Xilinx / merlin-compiler
  ☆57Updated last year
• Xilinx / xacc
  Heterogeneous Accelerated Computed Cluster (HACC) Resources Page
  ☆20Updated last week
• StanfordAHA / aha
  ☆52Updated this week