engjefersonsantiago / P4HLS
P4 compatible HLS modules
☆11Updated 7 years ago
Alternatives and similar repositories for P4HLS:
Users that are interested in P4HLS are comparing it to the libraries listed below
- An infrastructure for inline acceleration of network applications☆30Updated 3 years ago
- ☆14Updated 2 years ago
- ☆31Updated 9 years ago
- SmartNIC☆14Updated 6 years ago
- An Agile Chisel-Based SoC Design Framework☆26Updated 3 years ago
- A Programmable Hardware Architecture for Network Transport Logic☆35Updated 3 years ago
- ☆45Updated 2 years ago
- ☆19Updated 4 years ago
- ☆33Updated 4 years ago
- An FPGA-based NetTLP adapter☆25Updated 5 years ago
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆11Updated last year
- ☆62Updated 2 months ago
- A Fast, Scalable and Programmable Packet Scheduler in Hardware☆38Updated 5 years ago
- Artifacts for ATC '22 paper "Faster Software Packet Processing on FPGA NICs with eBPF Program Warping"☆17Updated 2 years ago
- Networking Template Library for Vivado HLS☆28Updated 4 years ago
- IRN's packet processing logic synthesized using Xilinx Vivado HLS☆22Updated 6 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆22Updated 3 years ago
- Framework for FPGA-accelerated Middlebox Development☆43Updated 2 years ago
- corundum work on vu13p☆18Updated last year
- DUA, is a communication architecture that provides uniform access for FPGA to data center resources. Without being limited by machine bou…☆38Updated 2 years ago
- Modifications to GEM5 for running kernel bypass networking. (DPDK)☆15Updated last year
- ☆10Updated 2 years ago
- pcie-bench code for NetFPGA/VCU709 cards☆35Updated 6 years ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆101Updated 2 years ago
- DPDK Drivers for AMD OpenNIC☆24Updated last year
- HW/SW co-designed end-host RPC stack☆20Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆41Updated 7 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- ☆14Updated 7 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago