fpga-logi / logi-hardLinks
All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc)
☆31Updated 9 years ago
Alternatives and similar repositories for logi-hard
Users that are interested in logi-hard are comparing it to the libraries listed below
Sorting:
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated last month
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 5 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 4 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 7 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 7 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Updated 6 years ago
- example code for the logi-boards from pong chu HDL book☆30Updated 10 years ago
- An open-source VHDL library for FPGA design.☆32Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- ☆20Updated 3 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 6 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Updated 2 years ago
- WISHBONE Builder☆15Updated 9 years ago
- Wishbone interconnect utilities☆44Updated 2 weeks ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆44Updated 4 years ago
- Example designs for the Spartan7 "S7 Mini" FPGA board☆29Updated 6 years ago
- Repository containing the DSP gateware cores☆14Updated last month
- Tester for IS61WV5128BLL-10BLI SRAM in Cmod A7-35T☆20Updated 7 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆45Updated 2 years ago
- Yosys Plugins☆22Updated 6 years ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆20Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆23Updated 2 years ago
- USB Full-Speed core written in migen/LiteX☆17Updated 6 years ago
- VHDL PCIe Transceiver☆32Updated 5 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Portable HyperRAM controller☆62Updated last year
- Featherweight RISC-V implementation☆53Updated 3 years ago
- demo project to show how to use vivado tcl scripts to do everything.☆17Updated 10 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆39Updated 5 years ago