fpga-logi / logi-hardLinks
All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc)
☆31Updated 9 years ago
Alternatives and similar repositories for logi-hard
Users that are interested in logi-hard are comparing it to the libraries listed below
Sorting:
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Updated 4 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆18Updated last month
- An open-source VHDL library for FPGA design.☆31Updated 3 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆42Updated 2 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 4 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- Repository containing the DSP gateware cores☆13Updated 3 weeks ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- ZPUino HDL implementation☆90Updated 7 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- Example designs for the Spartan7 "S7 Mini" FPGA board☆28Updated 6 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆29Updated 5 years ago
- USB Full-Speed core written in migen/LiteX☆17Updated 5 years ago
- example code for the logi-boards from pong chu HDL book☆29Updated 9 years ago
- ☆20Updated 3 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆38Updated 4 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Updated 6 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Updated 2 years ago
- Atom Hardware IDE☆13Updated 4 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated 2 weeks ago
- Simplified environment for litex☆14Updated 4 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- Library of reusable VHDL components☆28Updated last year