ymherklotz / vericertLinks
A formally verified high-level synthesis tool based on CompCert and written in Coq.
☆94Updated 2 months ago
Alternatives and similar repositories for vericert
Users that are interested in vericert are comparing it to the libraries listed below
Sorting:
- The source code to the Voss II Hardware Verification Suite☆56Updated last week
- A core language for rule-based hardware design 🦑☆164Updated last month
- Verilog development and verification project for HOL4☆27Updated 6 months ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆164Updated 3 weeks ago
- Time-sensitive affine types for predictable hardware generation☆146Updated 2 weeks ago
- FPGA synthesis tool powered by program synthesis☆52Updated last month
- ☆40Updated 4 years ago
- BTOR2 MLIR project☆26Updated last year
- Formal specification and verification of hardware, especially for security and privacy.☆127Updated 3 years ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- ☆30Updated 3 years ago
- Pono: A flexible and extensible SMT-based model checker☆116Updated this week
- A Modeling and Verification Platform for SoCs using ILAs☆81Updated last year
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- A Hardware Pipeline Description Language☆49Updated 4 months ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆91Updated last week
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.☆62Updated 10 years ago
- A formal semantics of the RISC-V ISA in Haskell☆170Updated 2 years ago
- A generic test bench written in Bluespec☆56Updated 4 years ago
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆31Updated 6 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Updated last year
- work in progress, playing around with btor2 in rust☆12Updated this week
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 5 months ago
- Automatically generate a compiler using equality saturation☆34Updated last year
- Galois RISC-V ISA Formal Tools☆60Updated 3 months ago
- ☆13Updated 4 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- Verilog AST☆21Updated last year
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14Updated 3 years ago