Alternatives and similar repositories for Shang:

Users that are interested in Shang are comparing it to the libraries listed below

• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆86Updated 2 years ago
• rdaly525 / coreir
  ☆102Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 6 months ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆100Updated 5 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆122Updated last year
• lana555 / dynamatic
  ☆86Updated last year
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆120Updated 10 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆111Updated this week
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆51Updated 5 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆73Updated 5 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆173Updated 8 months ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆153Updated 3 weeks ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆53Updated 4 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆168Updated last year
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 5 years ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆47Updated 2 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆47Updated 8 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆56Updated 8 months ago
• bu-icsg / dana
  Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
  ☆209Updated 5 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago