The Shang high-level synthesis framework
☆120May 29, 2014Updated 11 years ago
Alternatives and similar repositories for Shang
Users that are interested in Shang are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An open source high level synthesis (HLS) tool built on top of LLVM☆129Jun 11, 2024Updated last year
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆98Jan 29, 2026Updated 2 months ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 9 years ago
- A C to verilog compiler☆52Jun 20, 2015Updated 10 years ago
- Polyphony is Python based High-Level Synthesis compiler.☆110Apr 5, 2026Updated last week
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆223Dec 23, 2025Updated 3 months ago
- ☆30Oct 4, 2017Updated 8 years ago
- PandA-bambu public repository☆320Feb 10, 2026Updated 2 months ago
- ☆24Nov 10, 2020Updated 5 years ago
- ☆87Mar 5, 2024Updated 2 years ago
- Polyhedral High-Level Synthesis in MLIR☆35Mar 17, 2023Updated 3 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- Convert C files into Verilog☆21Jan 27, 2019Updated 7 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Aug 22, 2021Updated 4 years ago
- Vitis HLS LLVM source code and examples☆406Sep 30, 2025Updated 6 months ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Aug 26, 2024Updated last year
- ☆62Aug 4, 2023Updated 2 years ago
- ☆24May 8, 2015Updated 10 years ago
- Open-source FPGA research and prototyping framework.☆210Aug 8, 2024Updated last year
- Bridging polyhedral analysis tools to the MLIR framework☆119Sep 9, 2023Updated 2 years ago
- Benchmarks for High-Level Synthesis☆10Mar 17, 2023Updated 3 years ago
- A polyhedral compiler for hardware accelerators☆59Jul 24, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Accelerating SSSP for power-law graphs using an FPGA.☆23Mar 29, 2022Updated 4 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 5 years ago
- ☆14Jul 14, 2015Updated 10 years ago
- ☆40Sep 17, 2021Updated 4 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆136Apr 1, 2020Updated 6 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs (FPGA'18)☆170Nov 7, 2023Updated 2 years ago
- Veriloggen: A Mixed-Paradigm Hardware Construction Framework☆326Mar 8, 2026Updated last month
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆449Apr 5, 2026Updated last week
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Mar 29, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- DASS HLS Compiler☆31Oct 4, 2023Updated 2 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Nov 2, 2021Updated 4 years ago
- Flexible Intermediate Representation for RTL☆749Aug 20, 2024Updated last year
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆38Oct 20, 2020Updated 5 years ago
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆26Nov 14, 2022Updated 3 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- ☆20Mar 1, 2021Updated 5 years ago