Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.
☆22Jan 2, 2019Updated 7 years ago
Alternatives and similar repositories for SYMPL-GP-GPU-Compute-Engines
Users that are interested in SYMPL-GP-GPU-Compute-Engines are comparing it to the libraries listed below
Sorting:
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated this week
- A Simple to use build environment for parallella using yocto☆13Jul 28, 2025Updated 7 months ago
- Papers, Posters, Presentations, Documentation...☆19Jan 9, 2024Updated 2 years ago
- Verification Utilities for MyHDL☆17Oct 26, 2023Updated 2 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- RISC-V System on Chip Builder☆12Sep 27, 2020Updated 5 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- the actual epiphany backend☆20May 18, 2013Updated 12 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 3 years ago
- ☆16May 10, 2019Updated 6 years ago
- UVM testbench for verifying the Pulpino SoC☆12Mar 23, 2020Updated 5 years ago
- Audio filtering with pyfda and cocotb☆12Sep 24, 2020Updated 5 years ago
- ☆14Feb 24, 2025Updated last year
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆14Feb 22, 2019Updated 7 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Mar 23, 2018Updated 7 years ago
- UVM Clock and Reset Agent☆14Jun 29, 2017Updated 8 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- Parallel Array of Simple Cores. Multicore processor.☆100May 16, 2019Updated 6 years ago
- BOOM's Simulation Accelerator.☆13Dec 16, 2021Updated 4 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Jul 7, 2018Updated 7 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 5 years ago
- Lectures on Computer Architecture☆13Apr 11, 2022Updated 3 years ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- This is a myhdl test environment for the open-cores jpeg_encoder.☆18Oct 23, 2016Updated 9 years ago
- An executable specification of the RISCV ISA in L3.☆42Mar 1, 2019Updated 7 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated last week
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20May 4, 2017Updated 8 years ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 2 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆17Aug 3, 2021Updated 4 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆44May 26, 2021Updated 4 years ago
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 5 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- A home for Genesis2 sources.☆44Updated this week