jerry-D / SYMPL-GP-GPU-Compute-EnginesLinks
Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.
☆22Updated 6 years ago
Alternatives and similar repositories for SYMPL-GP-GPU-Compute-Engines
Users that are interested in SYMPL-GP-GPU-Compute-Engines are comparing it to the libraries listed below
Sorting:
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- An implementation of RISC-V☆44Updated 2 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated 2 weeks ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Xilinx Unisim Library in Verilog☆87Updated 5 years ago
- Advanced Debug Interface☆14Updated 10 months ago
- Open Processor Architecture☆26Updated 9 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- ☆63Updated 6 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- SoftCPU/SoC engine-V☆55Updated 8 months ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- SoCRocket - Core Repository☆38Updated 8 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 8 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆33Updated 3 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 2 months ago