jerry-D / SYMPL-GP-GPU-Compute-Engines
Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.
☆22Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for SYMPL-GP-GPU-Compute-Engines
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Open Processor Architecture☆26Updated 8 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- A Verilog Synthesis Regression Test☆34Updated 8 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆20Updated 3 weeks ago
- ☆63Updated 5 years ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- Demo SoC for SiliconCompiler.☆52Updated 3 weeks ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- ☆36Updated 2 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- SPI core☆15Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆60Updated 3 weeks ago
- Useful utilities for BAR projects☆30Updated 10 months ago
- Parallel Array of Simple Cores. Multicore processor.☆92Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- Advanced Debug Interface☆12Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆72Updated 5 years ago
- ☆18Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 4 months ago
- Collection of test cases for Yosys☆17Updated 2 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆62Updated 4 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Updated 8 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆35Updated last year