mattvenn / pyfda-cocotb-demoLinks
Audio filtering with pyfda and cocotb
☆12Updated 5 years ago
Alternatives and similar repositories for pyfda-cocotb-demo
Users that are interested in pyfda-cocotb-demo are comparing it to the libraries listed below
Sorting:
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆21Updated 2 years ago
- ☆26Updated 6 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆31Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- WISHBONE Interconnect☆11Updated 8 years ago
- A CIC filter implemented in Verilog☆23Updated 10 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated this week
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated last year
- UART cocotb module☆11Updated 4 years ago
- UART models for cocotb☆30Updated last month
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 7 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- SystemVerilog Linter based on pyslang☆31Updated 5 months ago
- hdmi-ts Project☆12Updated 8 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- ☆26Updated 2 years ago
- Wishbone interconnect utilities☆42Updated 8 months ago
- SpiceBind – spice inside HDL simulator☆55Updated 3 months ago
- Flip flop setup, hold & metastability explorer tool☆50Updated 2 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 8 months ago
- An example Python-based MDV testbench for apbi2c core☆30Updated last year
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- Open FPGA Modules☆24Updated last year