Alternatives and similar repositories for trollstigen-fpga

Users that are interested in trollstigen-fpga are comparing it to the libraries listed below

• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 11 months ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 8 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• dovebutch / tlv-comp
  ☆27Updated 4 months ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last month
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• fbrosser / DSP48E1-FP
  Project aimed at implementing floating point operators using the DSP48E1 slice.
  ☆29Updated 12 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆74Updated 6 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆18Updated 8 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆30Updated 8 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated 3 weeks ago
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 8 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆43Updated 2 weeks ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated 11 months ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 2 years ago