rbkettlewell / trollstigen-fpga
Open source fpga project leveraging vtr CAD flow.
☆26Updated last year
Related projects: ⓘ
- Open Processor Architecture☆26Updated 8 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 2 months ago
- A Verilog Synthesis Regression Test☆33Updated 5 months ago
- ☆22Updated 11 months ago
- Benchmarks for Yosys development☆21Updated 4 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 5 years ago
- ☆35Updated 2 years ago
- OpenFPGA☆33Updated 6 years ago
- A padring generator for ASICs☆22Updated last year
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆32Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Xilinx Unisim Library in Verilog☆68Updated 4 years ago
- Collection of test cases for Yosys☆17Updated 2 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- ☆12Updated 3 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- ☆28Updated 4 years ago
- ☆51Updated 2 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 3 years ago
- ☆19Updated this week
- Yosys Plugins☆20Updated 5 years ago
- mantle library☆42Updated last year
- OpenRISC processor IP core based on Tomasulo algorithm☆29Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- ☆25Updated 3 years ago
- An automatic clock gating utility☆40Updated 2 months ago
- Advanced Debug Interface☆12Updated last year
- ☆31Updated last year
- FGPU is a soft GPU architecture general purpose computing☆53Updated 3 years ago