Open source fpga project leveraging vtr CAD flow.
☆26Mar 4, 2023Updated 3 years ago
Alternatives and similar repositories for trollstigen-fpga
Users that are interested in trollstigen-fpga are comparing it to the libraries listed below
Sorting:
- firrtlator is a FIRRTL C++ library☆23Dec 15, 2016Updated 9 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Acorn Atom in minimal configuration for iCE40 HX8K board and ICOboard☆11Apr 30, 2023Updated 2 years ago
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 7 years ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- There are many RISC V projects on iCE40. This one is mine.☆14Jun 25, 2020Updated 5 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- A C++ template library for FPGAs on top of Xilinx Vivado HLS☆14Feb 2, 2017Updated 9 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 2 weeks ago
- C88 is Homebrew CPU that has a ram that is only 8x8 Bits in size. It'll fit on a papilio one 500k which has enough pins for all the switc…☆18Jun 1, 2021Updated 4 years ago
- ☆105Jun 27, 2022Updated 3 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆20Dec 5, 2023Updated 2 years ago
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Jan 2, 2019Updated 7 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- TLUT tool flow for parameterised configurations for FPGAs☆16Aug 5, 2024Updated last year
- Support for zScale on Spartan6 FPGAs☆15Aug 3, 2015Updated 10 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆12Jan 15, 2017Updated 9 years ago
- The source code that empowers OpenROAD Cloud☆12Jun 29, 2020Updated 5 years ago
- ☆16Aug 21, 2019Updated 6 years ago
- Not Another Range Library☆39Mar 9, 2014Updated 12 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 6 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- R package providing Asio C++ library header files☆14Nov 26, 2025Updated 3 months ago
- ☆16May 10, 2019Updated 6 years ago
- 1st Testwafer for LibreSilicon☆15May 24, 2019Updated 6 years ago
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- A universal control panel for Video for Linux Two (V4L2) devices.☆14Mar 30, 2020Updated 5 years ago
- HDMI Expansion Modules compatible with the Pmod standard☆11Apr 5, 2018Updated 7 years ago
- ☆13Sep 30, 2020Updated 5 years ago
- VexRiscv-SMP integration test with LiteX.☆26Nov 16, 2020Updated 5 years ago
- MIPI testing with LiteX on CrossLink-NX☆14Jan 29, 2026Updated last month
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆18Nov 15, 2019Updated 6 years ago
- My pergola FPGA projects☆30Jun 23, 2021Updated 4 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Jan 16, 2026Updated last month