☆15May 10, 2019Updated 6 years ago
Alternatives and similar repositories for uvm_reg_to_ipxact
Users that are interested in uvm_reg_to_ipxact are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆65Jan 28, 2026Updated 2 months ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated last year
- IPXACT Register Map Generator☆11May 9, 2021Updated 4 years ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- Contains examples to start with Kactus2.☆23Aug 5, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 3 years ago
- Useful UVM extensions☆27Jul 10, 2024Updated last year
- ☆12May 31, 2016Updated 9 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 6 years ago
- FTDI USB driver with bitbang mode☆13Dec 5, 2013Updated 12 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- SystemVerilog VIP for AMBA APB protocol☆86Nov 11, 2021Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- UVM register utility generation by inputting xls table☆39Aug 22, 2023Updated 2 years ago
- This example demonstrates the use of the Generic Interrupt Controller (GIC) in a baremetal environment.☆14Apr 2, 2024Updated 2 years ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 6 years ago
- A utility for processing command line arguments☆16Dec 19, 2025Updated 3 months ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Mar 23, 2018Updated 8 years ago
- Library for complex bitfields☆19May 25, 2024Updated last year
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 10 years ago
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 5 months ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Apr 10, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verification IP for UART protocol☆24Aug 3, 2020Updated 5 years ago
- ☆14Feb 24, 2025Updated last year
- Novel GUI Based UVM Testbench Template Builder☆152Apr 14, 2021Updated 5 years ago
- Reflection API for SystemVerilog☆15Mar 30, 2026Updated 2 weeks ago
- YAMM package repository☆32Mar 20, 2023Updated 3 years ago
- UVM Clock and Reset Agent☆14Jun 29, 2017Updated 8 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- ☆21May 18, 2018Updated 7 years ago
- SystemVerilog wrapper over the Verilog Programming Interface (VPI)☆12Jun 3, 2025Updated 10 months ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)☆11Apr 9, 2015Updated 11 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- IP-XACT XML binding library☆16Jun 23, 2016Updated 9 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- SystemVerilog Logger☆19Apr 6, 2026Updated last week
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 5 months ago