ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor
☆11Aug 23, 2017Updated 9 years ago
Alternatives and similar repositories for DualCoreProcessor
Users that are interested in DualCoreProcessor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware implementation of the ChaCha20-Poly1305 AEAD construction☆14Oct 8, 2020Updated 6 years ago
- A simple, working, 32-bit ALU design.☆14Dec 26, 2014Updated 11 years ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Mar 23, 2018Updated 8 years ago
- Parallel Array of Simple Cores. Multicore processor.☆101May 16, 2019Updated 7 years ago
- Computer Engineering Senior Project. Machine Learning High Frequency Stock Trading Algorithm on an FPGA☆17Dec 4, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Audio filtering with pyfda and cocotb☆13Sep 24, 2020Updated 6 years ago
- Cobra-W -> Cobra-RE 将进一步提升漏洞发现的准确性并降低漏报率（弃坑了）☆16Aug 15, 2020Updated 6 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 9 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Oct 19, 2026Updated last week
- Convert json descriptions of quant algorithms to verilog HDL.☆15Jul 3, 2020Updated 6 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.☆16Apr 1, 2018Updated 8 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- ☆18Sep 2, 2020Updated 6 years ago
- ☆10Oct 14, 2019Updated 7 years ago
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧，控制DA输出相应正弦信号☆10Jul 10, 2019Updated 7 years ago
- Simple Python module to call termux-api by subprocess.☆13May 13, 2025Updated last year
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 10 years ago
- This is a myhdl test environment for the open-cores jpeg_encoder.☆19Oct 23, 2016Updated 10 years ago
- Theia: ray graphic processing unit☆22Jul 17, 2014Updated 12 years ago
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 8 years ago
- FPGA, CuDNN/CUDA & C++ Hybrid infrastructure for ultra low-latency algorithmic trading. Implements market data parsing, order book manage…☆26Apr 24, 2026Updated 6 months ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Jan 2, 2019Updated 7 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 8 years ago
- The purpose of this unit is to introduce you to the measurement and analysis of electrical activity generated by skeletal muscle, includi…☆17Dec 26, 2021Updated 4 years ago
- 编译原理课程实践中用于测试的代码☆10Jun 9, 2021Updated 5 years ago
- 根据最近看的一本书编写的对应RTL以及Testbench☆20Mar 12, 2017Updated 9 years ago
- An Arduino-based speech synthesizer just like Stephen Hawking.☆14Feb 23, 2015Updated 11 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Synchronous FIFO design & verification using systemVerilog Assertions☆21Aug 3, 2021Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆22May 4, 2017Updated 9 years ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 3 years ago
- A Kubernetes cluster to learn Kubernetes. It includes Argo CD, Grafana, Prometheus, Loki, Tempo, Phlare and VictoriaMetrics.☆11Updated this week
- A scala based simulator for circuits described by a LoFirrtl file☆51Jan 12, 2023Updated 3 years ago
- EECS 151/251A FPGA Project Skeleton for Spring 2020☆12May 6, 2020Updated 6 years ago
- SystemVerilog、Verilog、UVM☆17Jun 23, 2020Updated 6 years ago