briandong / regModelLinks
This script builds the UVM register model, based on pre-defined address map in markdown (mk) style
☆12Updated 7 years ago
Alternatives and similar repositories for regModel
Users that are interested in regModel are comparing it to the libraries listed below
Sorting:
- UVM Clock and Reset Agent☆13Updated 8 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 4 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- Generate UVM testbench framework template files with Python 3☆26Updated 5 years ago
- ☆13Updated last year
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆12Updated 10 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- ☆16Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- ☆26Updated 4 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- ☆12Updated 9 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆32Updated 2 months ago
- ☆14Updated 6 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated last year
- Contains commonly used UVM components (agents, environments and tests).☆29Updated 6 years ago
- Useful UVM extensions☆24Updated last year
- Verification IP for UART protocol☆19Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆21Updated 5 years ago
- ☆11Updated 9 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- A mock framework for use with SVUnit☆19Updated 2 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago