Alternatives and similar repositories for regModel:

Users that are interested in regModel are comparing it to the libraries listed below

• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆12Updated 9 years ago
• imokanj / clk_rst_agent
  UVM Clock and Reset Agent
  ☆13Updated 7 years ago
• taichi-ishitani / tvip-common
  ☆12Updated 6 months ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆14Updated 6 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆14Updated 3 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆25Updated 5 years ago
• seabeam / yuu_clock
  UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available
  ☆10Updated 4 years ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆14Updated 4 years ago
• amiq-consulting / cagt
  Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …
  ☆12Updated 9 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆10Updated 4 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆18Updated 4 years ago
• imokanj / gpio_agent
  General Purpose I/O agent written in UVM
  ☆14Updated 7 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆18Updated 5 months ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆16Updated 4 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆15Updated 4 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 6 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆22Updated 6 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆26Updated 4 years ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆23Updated 3 weeks ago
• letitbe0201 / AXI-DMA-master-verification
  ☆23Updated 3 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆26Updated 3 weeks ago
• JakodYuan / SVK-AMBA-VIP
  Simple AMBA VIP, Include axi/ahb/apb
  ☆15Updated 6 months ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆31Updated 4 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆21Updated 6 months ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆28Updated 2 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago