Alternatives and similar repositories for regModel

Users that are interested in regModel are comparing it to the libraries listed below

• imokanj / clk_rst_agent
  UVM Clock and Reset Agent
  ☆14Updated 8 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆27Updated 6 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 7 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆13Updated 10 years ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆14Updated 5 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆17Updated 4 years ago
• seabeam / yuu_clock
  UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available
  ☆10Updated 5 years ago
• taichi-ishitani / tvip-common
  ☆14Updated last year
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆32Updated 5 years ago
• amiq-consulting / cagt
  Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …
  ☆13Updated 10 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated this week
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆21Updated 5 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 10 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• kumarrishav14 / arm_watchdog
  Verification IP for Watchdog
  ☆12Updated 4 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆26Updated 7 years ago
• svunit / svmock
  A mock framework for use with SVUnit
  ☆19Updated 2 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• imokanj / gpio_agent
  General Purpose I/O agent written in UVM
  ☆18Updated 8 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆31Updated 7 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆26Updated last year
• dpretet / svlogger
  SystemVerilog Logger
  ☆19Updated 3 months ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆35Updated 5 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 6 years ago
• mingzhang952 / uvm_auto
  uvm auto generator
  ☆24Updated 7 years ago
• JoseIuri / UVM_Python
  This repository contains an example of the connection between an UVM Testbench and a Python reference model.
  ☆12Updated 6 years ago
• zhouzaixin / arm_soc
  ☆14Updated 6 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆12Updated 5 years ago