franzflasch / leiwand_rv32
RISC-V RV32I CPU written in verilog
☆10Updated 4 years ago
Alternatives and similar repositories for leiwand_rv32:
Users that are interested in leiwand_rv32 are comparing it to the libraries listed below
- HDMI + GPU-pipeline + FFT☆13Updated 9 years ago
- ☆33Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated this week
- ☆18Updated 4 years ago
- Advanced Debug Interface☆14Updated 3 months ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- SCARV: a side-channel hardened RISC-V platform☆26Updated 2 years ago
- Program to scan for malicious FPGA designs.☆14Updated 4 years ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Updated 2 years ago
- ☆10Updated 4 years ago
- Open Source AES☆31Updated last year
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Basic Verilog Ethernet core and C driver functions☆11Updated 2 months ago
- ☆23Updated 7 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- Dual RISC-V DISC with integrated eFPGA☆16Updated 3 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- a small simple slow serial FPGA core☆16Updated 4 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 4 months ago
- ☆13Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated last month
- ☆13Updated last month
- The source code that empowers OpenROAD Cloud☆12Updated 4 years ago