Alternatives and similar repositories for Bossa

Users that are interested in Bossa are comparing it to the libraries listed below

• pku-liang / ksim
  ☆49Updated 10 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆37Updated last year
• miaochenlu / Gem5_tutorials
  ☆22Updated 2 weeks ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆34Updated last year
• pku-liang / Hestia
  ☆17Updated 7 months ago
• CMU-SAFARI / Pythia-HDL
  Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …
  ☆17Updated 4 years ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆33Updated 10 months ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆44Updated 2 years ago
• zeal4u / PMP
  About the source code of "Merging Similar Patterns for Hardware Prefetching" paper, which is accepted in MICRO 2022.
  ☆14Updated 2 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 3 years ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆24Updated last week
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated last month
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• observerw / ChiseLLM
  Reasoning LLMs optimized for Chisel code generation
  ☆21Updated 5 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆58Updated 3 years ago
• SwarmArch / sim
  ordspecsim: The Swarm architecture simulator
  ☆24Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆43Updated 5 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• PrincetonUniversity / maple
  MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…
  ☆21Updated last year
• cry-daniel / Computer-Architecture-Learning
  ☆65Updated 2 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆30Updated 5 years ago
• WukLab / FPGA-OS
  ☆35Updated 4 years ago
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆24Updated last year
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆29Updated this week
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆13Updated 2 years ago
• comparch-security / spike-cache
  Spike with a coherence supported cache model
  ☆14Updated last year