gjlies / configgpgpuView external linksLinks
A configurable general purpose graphics processing unit for
☆12May 18, 2019Updated 6 years ago
Alternatives and similar repositories for configgpgpu
Users that are interested in configgpgpu are comparing it to the libraries listed below
Sorting:
- ☆14Feb 24, 2025Updated 11 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Jan 27, 2026Updated 2 weeks ago
- SPIR-V fragment shader GPU core based on RISC-V☆43May 26, 2021Updated 4 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Ratatoskr NoC Simulator☆29Apr 13, 2021Updated 4 years ago
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 4 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- ☆11Jul 28, 2022Updated 3 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Jan 19, 2021Updated 5 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- 位宽和深度可定制的异步FIFO☆13May 29, 2024Updated last year
- ☆13Apr 1, 2017Updated 8 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- SoC based on RISC V ISA☆10Apr 22, 2022Updated 3 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆21Mar 25, 2025Updated 10 months ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 5 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆24Updated this week
- ☆17Dec 21, 2020Updated 5 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- ☆16May 10, 2019Updated 6 years ago
- DMA core compatible with AHB3-Lite☆10Mar 30, 2019Updated 6 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Direct Access Memory for MPSoC☆13Jan 27, 2026Updated 2 weeks ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- ☆15May 13, 2025Updated 9 months ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 3 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- ☆21Sep 26, 2025Updated 4 months ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 11 years ago