gjlies / configgpgpuLinks
A configurable general purpose graphics processing unit for
☆11Updated 6 years ago
Alternatives and similar repositories for configgpgpu
Users that are interested in configgpgpu are comparing it to the libraries listed below
Sorting:
- ☆14Updated 9 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last month
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- Network on Chip for MPSoC☆28Updated this week
- An Open Source Link Protocol and Controller☆27Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated this week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 2 years ago
- ☆20Updated last week
- ☆13Updated 7 months ago
- NoC based MPSoC☆11Updated 11 years ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- Direct Access Memory for MPSoC☆13Updated this week
- ☆13Updated 2 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- RTL implementation of a ray-tracing GPU☆13Updated 13 years ago
- RISC-V IOMMU in verilog☆20Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Theia: ray graphic processing unit☆20Updated 11 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Updated 11 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 10 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- Advanced Debug Interface☆14Updated 10 months ago
- The official NaplesPU hardware code repository☆20Updated 6 years ago