alice820621 / SystemVerilog-Implementation-of-DDR3-ControllerView external linksLinks
The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieved via a specialized test bench and connected to provided AHB by a SystemVerilog interface.
☆23Jul 6, 2018Updated 7 years ago
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