jbush001 / PASCLinks
Parallel Array of Simple Cores. Multicore processor.
☆99Updated 6 years ago
Alternatives and similar repositories for PASC
Users that are interested in PASC are comparing it to the libraries listed below
Sorting:
- Yet Another RISC-V Implementation☆98Updated last year
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆80Updated 6 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆104Updated 7 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- ☆63Updated 6 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆89Updated 6 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 5 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 10 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Open Processor Architecture☆26Updated 9 years ago
- An Open Source configuration of the Arty platform☆132Updated last year
- FuseSoC standard core library☆148Updated 5 months ago
- OmniXtend cache coherence protocol☆82Updated 5 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago