jbush001 / PASCLinks
Parallel Array of Simple Cores. Multicore processor.
☆99Updated 6 years ago
Alternatives and similar repositories for PASC
Users that are interested in PASC are comparing it to the libraries listed below
Sorting:
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆102Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Yet Another RISC-V Implementation☆97Updated 11 months ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 4 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- ☆64Updated 6 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆184Updated 8 months ago
- FOS - FPGA Operating System☆71Updated 4 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆32Updated 3 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- OpenSPARC-based SoC☆69Updated 11 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago