Alternatives and similar repositories for coriolis

Users that are interested in coriolis are comparing it to the libraries listed below

• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆14Updated 3 years ago
• chipsalliance / f4pga-xc7-bram-patch
  Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.
  ☆19Updated 4 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 7 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 5 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆22Updated 4 years ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆38Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL
  ☆32Updated last year
• ydnatag / nmigen-cocotb
  cocotb extension for nMigen
  ☆17Updated 3 years ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 7 years ago
• chili-chips-ba / openCologne-PCIE
  The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…
  ☆55Updated last month
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• m-labs / nmigen-stdio
  Industry standard I/O for nMigen
  ☆12Updated 5 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• enjoy-digital / litesata_axiom
  ☆13Updated 5 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆34Updated 2 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 4 years ago
• semify-eda / go.debug
  Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
  ☆11Updated 4 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 3 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 6 months ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆32Updated 5 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆34Updated last year
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 4 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• apertus-open-source-cinema / axiom-micro-gateware
  gateware for the main fpga, including a hispi decoder and image processing
  ☆13Updated 7 years ago
• buttercutter / noc
  A simple spidergon network-on-chip with wormhole switching feature
  ☆12Updated 4 years ago