Alternatives and similar repositories for Verilog_projects

Users that are interested in Verilog_projects are comparing it to the libraries listed below

• iammituraj / fifo
  Synchronous FIFOs designed in Verilog/System Verilog.
  ☆22Updated last week
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆22Updated last week
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆42Updated 11 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 8 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆28Updated 5 months ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆40Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 9 months ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 9 months ago
• bradgrantham / alice5
  SPIR-V fragment shader GPU core based on RISC-V
  ☆42Updated 4 years ago
• himanshu5-prog / vortexGPU
  ☆22Updated 4 years ago
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 5 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated 5 months ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆28Updated 4 years ago
• corundum / verilog-pcie
  Verilog PCI express components
  ☆24Updated 2 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• b224hisl / rioschip
  ☆32Updated 2 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆14Updated 8 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆17Updated 3 years ago
• PacoReinaCampo / vhdl2verilog
  Hardware Description Language Translator
  ☆17Updated 5 months ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• SLink-Protocol / S-Link
  An Open Source Link Protocol and Controller
  ☆27Updated 4 years ago
• embedded-explorer / Open-Source-RTL-Design
  This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
  ☆38Updated 4 years ago