bharathk005 / Verilog_projects

Related projects: ⓘ

• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆14Updated last month
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  Hamming ECC Encoder and Decoder to protect memories
  ☆26Updated 3 months ago
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  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated 10 months ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆31Updated 10 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆33Updated 3 years ago
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆17Updated 6 years ago
• corundum / verilog-ethernet
  Verilog Ethernet components for FPGA implementation
  ☆14Updated last year
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  ☆24Updated 3 years ago
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  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆56Updated 3 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆19Updated this week
• FPGA-Research-Manchester / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆24Updated 3 years ago
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  ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
  ☆4Updated last year
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  ☆29Updated 3 years ago
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  ☆19Updated 6 years ago
• freecores / ddr3_sdram
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  ☆18Updated 10 years ago
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  ☆29Updated 8 years ago
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  ☆15Updated 2 years ago
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  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
  ☆18Updated 9 years ago
• taneroksuz / fpu-sp
  IEEE 754 floating point library in system-verilog and vhdl
  ☆26Updated 4 months ago
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  ☆31Updated last year
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  ☆25Updated 2 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆15Updated 4 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆52Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆27Updated 5 years ago
• FPGA-Research-Manchester / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆13Updated 4 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆21Updated 5 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆28Updated 8 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆20Updated 6 years ago