Alternatives and similar repositories for Verilog_projects

Users that are interested in Verilog_projects are comparing it to the libraries listed below

• iammituraj / fifo
  Synchronous FIFOs designed in Verilog/System Verilog.
  ☆24Updated last month
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆22Updated last month
• ryanmacdonald / Ray-Tracing-GPU
  RTL implementation of a ray-tracing GPU
  ☆13Updated 13 years ago
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 5 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 10 months ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆38Updated 7 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆29Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 10 months ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆43Updated 11 years ago
• bradgrantham / alice5
  SPIR-V fragment shader GPU core based on RISC-V
  ☆42Updated 4 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• mjkkirschner / simpleGPUCore
  verilog/FPGA hardware description for very simple GPU
  ☆16Updated 6 years ago
• himanshu5-prog / vortexGPU
  ☆23Updated 4 years ago
• gjlies / configgpgpu
  A configurable general purpose graphics processing unit for
  ☆11Updated 6 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 10 months ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆19Updated last year
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆41Updated 4 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 2 years ago
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆18Updated 8 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆15Updated 8 years ago
• furkanturan / lowrisc-zed
  LowRISC port to Zedboard
  ☆13Updated 8 years ago
• SLink-Protocol / S-Link
  An Open Source Link Protocol and Controller
  ☆27Updated 4 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆51Updated 4 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 8 years ago