jix / kissat_extras
A fork of the Kissat SAT solver with additional features. Supports incremental solving.
☆13Updated 2 years ago
Alternatives and similar repositories for kissat_extras:
Users that are interested in kissat_extras are comparing it to the libraries listed below
- Hardware Model Checker☆27Updated this week
- ☆12Updated 2 years ago
- Random Generator of Btor2 Files☆9Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆27Updated 6 months ago
- CoreIR Symbolic Analyzer☆63Updated 4 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆21Updated 2 years ago
- A generic parser and tool package for the BTOR2 format.☆41Updated last month
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆14Updated 8 years ago
- ☆14Updated 4 years ago
- AIGER And-Inverter-Graph Library☆65Updated last month
- Research paper based on or related to ABC.☆24Updated 2 weeks ago
- BTOR2 MLIR project☆22Updated last year
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆18Updated 2 weeks ago
- The source code to the Voss II Hardware Verification Suite☆53Updated this week
- Reads a state transition system and performs property checking☆76Updated 2 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆16Updated 4 months ago
- ☆11Updated 4 years ago
- ILA Model Database☆22Updated 4 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Updated 5 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- The HW-CBMC and EBMC Model Checkers for Verilog☆63Updated this week
- RISC-V Formal in Chisel☆10Updated 9 months ago
- Pono: A flexible and extensible SMT-based model checker☆89Updated this week
- ☆16Updated 6 months ago
- A Formal Verification Framework for Chisel☆18Updated 9 months ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆11Updated 5 years ago
- Fast Symbolic Repair of Hardware Design Code☆21Updated last week
- C++ header-only exact synthesis library☆15Updated 2 years ago
- An advanced header-only exact synthesis library☆24Updated 2 years ago