jix / kissat_extrasLinks
A fork of the Kissat SAT solver with additional features. Supports incremental solving.
☆14Updated 2 years ago
Alternatives and similar repositories for kissat_extras
Users that are interested in kissat_extras are comparing it to the libraries listed below
Sorting:
- Collection for submission (Hardware Model Checking Benchmark)☆10Updated 7 months ago
- ☆12Updated 2 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆32Updated 10 months ago
- Random Generator of Btor2 Files☆10Updated last year
- Hardware Formal Verification Tool☆52Updated this week
- LLM Evaluation Benchmark on Hardware Formal Verification☆21Updated 2 months ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 4 months ago
- A high-efficiency hybrid solving CEC algorithm☆11Updated 2 years ago
- ☆16Updated 4 years ago
- Research paper based on or related to ABC.☆43Updated this week
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Updated 8 months ago
- A generic parser and tool package for the BTOR2 format.☆41Updated last month
- AMulet 2. - A better AIG Multiplier Examination Tool☆25Updated 2 years ago
- BTOR2 MLIR project☆25Updated last year
- CoreIR Symbolic Analyzer☆73Updated 4 years ago
- ☆10Updated 5 years ago
- ☆19Updated 10 months ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 6 years ago
- AIGER And-Inverter-Graph Library☆78Updated this week
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆18Updated last month
- ☆12Updated 7 years ago
- Open-source RTL logic simulator with CUDA acceleration☆19Updated last week
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆15Updated 6 years ago
- ☆13Updated 4 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- ☆18Updated 11 months ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆72Updated this week
- Integer Multiplier Generator for Verilog☆23Updated last year
- ☆13Updated 4 years ago
- ☆31Updated last year