Alternatives and similar repositories for I99T

Users that are interested in I99T are comparing it to the libraries listed below

• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆62Updated last month
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆57Updated 9 months ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆43Updated last year
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆28Updated 5 years ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆213Updated last week
• lnis-uofu / LSOracle
  IDEA project source files
  ☆109Updated last month
• nbulsi / also
  A logic synthesis tool
  ☆82Updated last month
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆57Updated 4 months ago
• The-OpenROAD-Project / asap7
  ☆197Updated 7 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• zshi0616 / python-deepgate
  ☆23Updated last year
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆51Updated last year
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆34Updated 2 months ago
• DfX-NYUAD / GNNUnlock
  ☆16Updated 3 years ago
• bluesceada / iscas89_hl_verilog
  Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
  ☆14Updated 3 years ago
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆133Updated 2 months ago
• NVlabs / INSTA
  ☆88Updated 3 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆96Updated 3 months ago
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆22Updated 11 months ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆77Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆90Updated 2 months ago
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆53Updated 2 years ago
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆15Updated 8 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆97Updated 3 years ago
• ABKGroup / TritonRoute-WXL
  ☆34Updated 4 years ago
• pkuzjx / eda-collection
  ☆106Updated 5 years ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆29Updated last year
• zshi0616 / DeepGate2
  ☆29Updated last year