cad-polito-it / I99T
ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
☆47Updated last year
Related projects ⓘ
Alternatives and complementary repositories for I99T
- Collection of digital hardware modules & projects (benchmarks)☆33Updated last week
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆36Updated last month
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆23Updated 4 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆32Updated 4 months ago
- IDEA project source files☆98Updated 2 weeks ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆75Updated 3 weeks ago
- ☆100Updated 4 months ago
- ☆38Updated 2 months ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 7 years ago
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆75Updated 6 months ago
- DATC RDF☆48Updated 4 years ago
- ☆14Updated 2 years ago
- GPU-based logic synthesis tool☆68Updated 4 months ago
- Artificial Netlist Generator☆33Updated 8 months ago
- ☆36Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆97Updated 8 months ago
- ☆99Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆73Updated 7 months ago
- ☆36Updated 7 months ago
- ☆21Updated 4 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆33Updated last year
- VLSI EDA Global Router☆68Updated 6 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆47Updated 2 weeks ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- EPFL logic synthesis benchmarks☆166Updated 2 months ago
- Material for OpenROAD Tutorial at DAC 2020☆46Updated last year
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆28Updated last month
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆13Updated 2 years ago
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆99Updated 4 months ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆17Updated last year