cad-polito-it / I99TLinks
ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
☆65Updated 6 months ago
Alternatives and similar repositories for I99T
Users that are interested in I99T are comparing it to the libraries listed below
Sorting:
- Collection of digital hardware modules & projects (benchmarks)☆69Updated last week
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆58Updated 10 months ago
- EPFL logic synthesis benchmarks☆217Updated this week
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆29Updated 5 years ago
- Artificial Netlist Generator☆44Updated last year
- IDEA project source files☆109Updated last month
- ☆89Updated 5 months ago
- ☆208Updated 8 months ago
- ☆25Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- A logic synthesis tool☆82Updated 2 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆36Updated 4 months ago
- ☆27Updated last year
- reference block design for the ASAP7nm library in Cadence Innovus☆51Updated last year
- ☆107Updated 5 years ago
- DATC RDF☆50Updated 5 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆107Updated last year
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆15Updated 3 years ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆136Updated 3 months ago
- ☆44Updated last year
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆99Updated 4 months ago
- Rsyn – An Extensible Physical Synthesis Framework☆132Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆86Updated 6 months ago
- ☆77Updated 5 months ago
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆84Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆138Updated 2 years ago
- GPU-based logic synthesis tool☆96Updated last week
- ☆16Updated 3 years ago
- Research paper based on or related to ABC.☆59Updated last week
- GNN-RE datasets for circuit recognition☆54Updated 2 years ago