coherent17 / 2024-ICCAD-Problem-BLinks
Power and Timing Optimization Using MBFF
☆17Updated 2 months ago
Alternatives and similar repositories for 2024-ICCAD-Problem-B
Users that are interested in 2024-ICCAD-Problem-B are comparing it to the libraries listed below
Sorting:
- ☆12Updated last year
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆44Updated 9 months ago
- ☆44Updated last year
- 2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …☆39Updated 2 months ago
- ☆16Updated 5 months ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆133Updated last month
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆41Updated 6 years ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆28Updated 2 years ago
- ☆20Updated 6 months ago
- Problem B: 3D Placement with D2D Vertical Connections☆10Updated 3 years ago
- Artificial Netlist Generator☆39Updated last year
- Rsyn – An Extensible Physical Synthesis Framework☆127Updated last year
- Mirror of the Si2 LEF/DEF parser (v5.8)☆16Updated 3 years ago
- IC-contest 2012~2024☆19Updated last year
- NTHU CS6135 VLSI Physical Design Automation (2022 Fall)☆16Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆54Updated 6 months ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆76Updated 11 months ago
- Timing prediction dataset download and instructions.☆15Updated 2 years ago
- VLSI EDA Global Router☆75Updated 7 years ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.☆21Updated 11 months ago
- RePlAce global placement tool☆236Updated 4 years ago
- Encoder-decoder based generative networks for static and transient thermal analysis☆21Updated 2 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- ☆34Updated 4 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆28Updated 3 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆31Updated 3 weeks ago
- ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino☆58Updated 2 months ago
- EPFL logic synthesis benchmarks☆203Updated 3 weeks ago
- The first version of TritonPart☆28Updated last year
- ☆11Updated last year