sharc-lab / FlowGNNLinks
A dataflow architecture for universal graph neural network inference via multi-queue streaming.
☆73Updated 2 years ago
Alternatives and similar repositories for FlowGNN
Users that are interested in FlowGNN are comparing it to the libraries listed below
Sorting:
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆40Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆82Updated last year
- ☆38Updated 2 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆135Updated last month
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated last year
- ☆56Updated 4 months ago
- RTL implementation of Flex-DPE.☆107Updated 5 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆111Updated 2 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆85Updated 3 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- ☆17Updated 10 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆38Updated 2 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆20Updated 2 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 4 months ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆146Updated 2 months ago
- This repo is to collect the state-of-the-art GNN hardware acceleration paper☆54Updated 4 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week
- HLS-based Graph Processing Framework on FPGAs☆147Updated 2 years ago
- ☆41Updated last year
- ☆28Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆39Updated 3 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago