sharc-lab / FlowGNNLinks
A dataflow architecture for universal graph neural network inference via multi-queue streaming.
☆73Updated 2 years ago
Alternatives and similar repositories for FlowGNN
Users that are interested in FlowGNN are comparing it to the libraries listed below
Sorting:
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- ☆40Updated 2 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 10 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆137Updated 2 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆65Updated 2 years ago
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- HLS-based Graph Processing Framework on FPGAs☆148Updated 2 years ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆87Updated 3 months ago
- ☆57Updated 5 months ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆112Updated 2 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated last year
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆20Updated 3 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆17Updated 11 months ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆44Updated 3 weeks ago
- An integrated CGRA design framework☆90Updated 5 months ago
- gem5 repository to study chiplet-based systems☆79Updated 6 years ago
- This repo is to collect the state-of-the-art GNN hardware acceleration paper☆54Updated 4 years ago
- A list of our chiplet simulaters☆34Updated 2 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆77Updated 6 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 4 months ago
- A graph linear algebra overlay☆51Updated 2 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆38Updated 2 years ago