DUTH RISC V Microprocessor for High Level Synthesis
☆10Jun 23, 2023Updated 2 years ago
Alternatives and similar repositories for DRIM4HLS
Users that are interested in DRIM4HLS are comparing it to the libraries listed below
Sorting:
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- Algorithmic C Machine Learning Library☆26Jan 6, 2026Updated 2 months ago
- Fast Floating Point Operators for High Level Synthesis☆24Feb 23, 2023Updated 3 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Jan 6, 2026Updated 2 months ago
- DaCH: dataflow cache for high-level synthesis.☆20Jul 27, 2023Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Feb 6, 2020Updated 6 years ago
- Essential Tools for Programming☆10Aug 17, 2015Updated 10 years ago
- SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC☆15Jan 23, 2020Updated 6 years ago
- HLS for Networks-on-Chip☆39Feb 18, 2021Updated 5 years ago
- Explore Graph Convolutional Networks☆17Jul 6, 2023Updated 2 years ago
- ☆11Jul 16, 2020Updated 5 years ago
- A CNN model to to recognize Japanese adult video actress face☆13Dec 1, 2018Updated 7 years ago
- C++ System Development Kit for Nostr☆10Mar 13, 2025Updated last year
- A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS☆14Jan 30, 2024Updated 2 years ago
- Lemberg is a time-predictable VLIW processor optimized for performance.☆21May 8, 2013Updated 12 years ago
- 高级计算机体系结构记分牌算法实验☆13Dec 22, 2018Updated 7 years ago
- Nostr module for Qt☆11Jul 24, 2023Updated 2 years ago
- Collection of kernel accelerators optimised for LLM execution☆27Feb 26, 2026Updated 3 weeks ago
- ☆22Oct 26, 2022Updated 3 years ago
- A scalable High-Level Synthesis framework on MLIR☆291May 15, 2024Updated last year
- Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"☆15Sep 12, 2022Updated 3 years ago
- ☆22Nov 3, 2025Updated 4 months ago
- ElGamal cryptosystem for JavaScript.☆27May 26, 2016Updated 9 years ago
- ☆10May 26, 2023Updated 2 years ago
- 2020 xilinx summer school☆19Aug 13, 2020Updated 5 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 6 years ago
- ☆19Aug 9, 2022Updated 3 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Sep 4, 2025Updated 6 months ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated 2 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Feb 2, 2026Updated last month
- ☆72Feb 16, 2023Updated 3 years ago
- Minimal microprocessor☆21Jul 1, 2017Updated 8 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- ☆20Dec 29, 2014Updated 11 years ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆66Dec 18, 2024Updated last year
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆30Feb 23, 2024Updated 2 years ago
- ☆16Jun 25, 2016Updated 9 years ago
- ☆13Aug 1, 2024Updated last year