ic-lab-duth / DRIM4HLS
DUTH RISC V Microprocessor for High Level Synthesis
☆10Updated last year
Related projects ⓘ
Alternatives and complementary repositories for DRIM4HLS
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆22Updated 5 years ago
- ☆13Updated last year
- ☆21Updated last month
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆19Updated last year
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆23Updated last month
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆19Updated this week
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- DASS HLS Compiler☆27Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆18Updated last year
- An HBM FPGA based SpMV Accelerator☆9Updated 2 months ago
- ☆3Updated 3 years ago
- ☆32Updated 5 years ago
- Benchmarks for Approximate Circuit Synthesis☆13Updated 4 years ago
- ☆33Updated 3 years ago
- ACM TODAES Best Paper Award, 2022☆24Updated last year
- NPUsim: Full-system, Cycle-accurate, Value-aware NPU Simulator☆24Updated last week
- Algorithmic C Machine Learning Library☆22Updated 3 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆21Updated last month
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago