ic-lab-duth / DRIM4HLS
DUTH RISC V Microprocessor for High Level Synthesis
☆10Updated last year
Alternatives and similar repositories for DRIM4HLS:
Users that are interested in DRIM4HLS are comparing it to the libraries listed below
- ☆24Updated 5 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆23Updated 9 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆27Updated 3 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆28Updated 2 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Ratatoskr NoC Simulator☆23Updated 3 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- HLS for Networks-on-Chip☆33Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Algorithmic C Machine Learning Library☆22Updated last month
- ACM TODAES Best Paper Award, 2022☆24Updated last year
- ☆3Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆40Updated 8 months ago
- Stencil with Optimized Dataflow Architecture☆12Updated 11 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆25Updated 3 weeks ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated 11 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- ☆15Updated last year
- ☆24Updated 4 months ago
- ☆33Updated 3 years ago
- sram/rram/mram.. compiler☆30Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆29Updated last year
- ☆53Updated last year