RatkoFri / MulApproxLinks
MulApprox - A comprehensive library of state-of-the-art approximate multipliers
☆30Updated 4 years ago
Alternatives and similar repositories for MulApprox
Users that are interested in MulApprox are comparing it to the libraries listed below
Sorting:
- Library of approximate arithmetic circuits☆55Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆85Updated last month
- ☆68Updated last week
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- ☆58Updated 5 years ago
- ☆60Updated 2 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 5 months ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- ☆65Updated 6 years ago
- ☆15Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 4 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆40Updated this week
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- A tool for synthesizing Verilog programs☆95Updated 2 weeks ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- ☆47Updated 3 months ago
- Verilog Implementation of 32-bit Floating Point Adder☆40Updated 5 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month
- IC implementation of TPU☆128Updated 5 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆73Updated this week
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago