Alternatives and similar repositories for CHIP-KNN:

Users that are interested in CHIP-KNN are comparing it to the libraries listed below

• pgroupATusc / GraphACT
  Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".
  ☆10Updated 4 years ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆20Updated 4 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆86Updated 5 months ago
• jasonlin316 / GCN-Inference-Acceleration-HLS
  An end-to-end GCN inference accelerator written in HLS
  ☆19Updated 2 years ago
• sharc-lab / DGNN-Booster
  ☆16Updated last year
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆69Updated 3 years ago
• KULeuven-MICAS / zigzag-imc
  HW accelerator mapping optimization framework for in-memory computing
  ☆22Updated last month
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆31Updated last week
• Accelergy-Project / processing-in-memory-design
  ☆26Updated 10 months ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 2 years ago
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆17Updated 2 years ago
• cornell-zhang / GraphLily
  A graph linear algebra overlay
  ☆51Updated last year
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
  ☆20Updated 2 months ago
• ic-lab-duth / FusedGCN4HLS
  Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
  ☆22Updated 2 years ago
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• linghaosong / Serpens
  An HBM FPGA based SpMV Accelerator
  ☆13Updated 6 months ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• mnnuahg / StamicCGRA
  A static dataflow CGRA with dynamic dataflow execution capability
  ☆10Updated 3 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆34Updated 4 years ago
• Xtra-Computing / ReGraph
  Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines
  ☆17Updated 2 years ago
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆17Updated 7 months ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆11Updated 10 months ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆22Updated last week
• neurosim / 3D_NeuroSim_V1.0
  Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration
  ☆22Updated 3 years ago
• sfu-arch / SpGEMM
  ☆34Updated 3 years ago
• fffasttime / AnyPackingNet
  ☆25Updated 2 months ago
• hpc-ulisboa / NDPmulator
  A Full-System Framework for Simulating NDP devices from Caches to DRAM
  ☆16Updated last year
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆30Updated 3 years ago