sharc-lab / FPGA_ECE8893
☆35Updated 2 weeks ago
Alternatives and similar repositories for FPGA_ECE8893:
Users that are interested in FPGA_ECE8893 are comparing it to the libraries listed below
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆73Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago
- eyeriss-chisel3☆40Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆78Updated 8 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆48Updated 3 weeks ago
- ☆59Updated last year
- ☆71Updated 2 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆13Updated 9 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆41Updated last month
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆56Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Open-source of MSD framework☆16Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated last month
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆122Updated last week
- ☆3Updated 3 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- ☆35Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆61Updated 3 months ago
- Eyeriss chip simulator☆36Updated 5 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆50Updated last month
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆70Updated 5 years ago
- ☆70Updated 5 years ago
- Verilog implementation of Softmax function☆62Updated 2 years ago