Alternatives and similar repositories for GNN-ARCH

Users that are interested in GNN-ARCH are comparing it to the libraries listed below

• jasonlin316 / GCN-Inference-Acceleration-HLS
  An end-to-end GCN inference accelerator written in HLS
  ☆18Updated 3 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆87Updated last year
• lsq314 / SpMM_TCAD
  ☆18Updated last year
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆73Updated 2 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• sharc-lab / DGNN-Booster
  ☆15Updated 2 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆81Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆113Updated 5 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆67Updated last month
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆43Updated 4 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 7 months ago
• groupsada / DeepBurning
  Automatic generation of FPGA-based learning accelerators for the neural network family
  ☆66Updated 5 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 4 years ago
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆18Updated 3 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆22Updated last year
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆94Updated 4 years ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆23Updated 11 months ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 3 years ago
• Xtra-Computing / ReGraph
  Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines
  ☆22Updated 3 years ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆17Updated last year
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 3 years ago
• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆51Updated last year
• pgroupATusc / GraphACT
  Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".
  ☆10Updated 5 years ago
• SFU-HiAccel / HiSpMV
  [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS
  ☆15Updated 2 months ago
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆39Updated 2 years ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆35Updated 3 years ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆157Updated this week
• tuna / tapa
  TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.
  ☆175Updated 2 months ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago