GraphSAINT / GNN-ARCHLinks
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
☆42Updated 4 years ago
Alternatives and similar repositories for GNN-ARCH
Users that are interested in GNN-ARCH are comparing it to the libraries listed below
Sorting:
- ☆20Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆74Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆16Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- ☆17Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆73Updated last month
- A list of our chiplet simulaters☆45Updated 6 months ago
- NeuraChip Accelerator Simulator☆15Updated last year
- An integrated CGRA design framework☆91Updated 9 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆36Updated 3 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆20Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- ☆42Updated last year
- Automatic generation of FPGA-based learning accelerators for the neural network family☆66Updated 6 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated this week
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆22Updated 3 years ago
- [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS☆18Updated 4 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- ☆35Updated 5 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆68Updated 2 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆147Updated 6 months ago