GraphSAINT / GNN-ARCHLinks
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
☆43Updated 4 years ago
Alternatives and similar repositories for GNN-ARCH
Users that are interested in GNN-ARCH are comparing it to the libraries listed below
Sorting:
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆75Updated 3 years ago
- ☆20Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- ☆16Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 3 months ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆22Updated 3 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆22Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆24Updated last year
- A list of our chiplet simulaters☆47Updated 7 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆97Updated 4 years ago
- NeuraChip Accelerator Simulator☆15Updated last year
- An integrated CGRA design framework☆91Updated 10 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆145Updated 7 months ago
- ☆17Updated 4 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆12Updated 5 years ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆23Updated last year
- RTL generator for SpGEMM☆10Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆93Updated 3 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆68Updated 2 years ago
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆39Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆177Updated 5 months ago
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆113Updated 9 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 7 months ago