GraphSAINT / GNN-ARCHLinks
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
☆40Updated 4 years ago
Alternatives and similar repositories for GNN-ARCH
Users that are interested in GNN-ARCH are comparing it to the libraries listed below
Sorting:
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- ☆17Updated 10 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- RTL implementation of Flex-DPE.☆108Updated 5 years ago
- ☆15Updated 2 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆18Updated 3 years ago
- An integrated CGRA design framework☆90Updated 4 months ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆20Updated 2 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- A list of our chiplet simulaters☆33Updated last month
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- ☆38Updated 2 months ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆67Updated 5 years ago
- ☆72Updated 2 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆19Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆22Updated 8 months ago
- Dataset for ML-guided Accelerator Design☆37Updated 8 months ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆51Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆75Updated last month
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆57Updated last month