ic-lab-duth / NoCpadLinks
HLS for Networks-on-Chip
☆35Updated 4 years ago
Alternatives and similar repositories for NoCpad
Users that are interested in NoCpad are comparing it to the libraries listed below
Sorting:
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆56Updated 10 months ago
- ☆34Updated 6 years ago
- ☆27Updated 5 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- ☆52Updated 6 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- Public release☆57Updated 5 years ago
- ☆77Updated 10 years ago
- A verilog implementation for Network-on-Chip☆75Updated 7 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- ☆29Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- Project repo for the POSH on-chip network generator☆49Updated 5 months ago
- ☆32Updated 2 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆26Updated last year
- ☆60Updated 2 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 2 weeks ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 7 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated 3 weeks ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆30Updated last year
- ☆17Updated 3 months ago
- ☆15Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated this week
- cycle accurate Network-on-Chip Simulator☆29Updated 2 years ago