HLS for Networks-on-Chip
☆39Feb 18, 2021Updated 5 years ago
Alternatives and similar repositories for NoCpad
Users that are interested in NoCpad are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- System-on-Chip Interconnection Network - Simulation Environment (front-end)☆15Oct 5, 2023Updated 2 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆190Nov 18, 2024Updated last year
- HLS code for Network on Chip (NoC)☆22Sep 11, 2020Updated 5 years ago
- General Purpose AXI Direct Memory Access☆63May 12, 2024Updated last year
- ☆11Oct 28, 2021Updated 4 years ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Jun 23, 2023Updated 2 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆147Mar 19, 2018Updated 8 years ago
- Fast Floating Point Operators for High Level Synthesis☆24Feb 23, 2023Updated 3 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- Ratatoskr NoC Simulator☆29Apr 13, 2021Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- DUTH RISC-V Microprocessor☆25Dec 4, 2024Updated last year
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆33Jan 4, 2026Updated 2 months ago
- ☆13Aug 1, 2024Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆116Sep 24, 2025Updated 5 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆406Updated this week
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆13Sep 9, 2022Updated 3 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 10 months ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 8 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- Network on Chip Simulator☆306Oct 26, 2025Updated 4 months ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Apr 17, 2016Updated 9 years ago
- Stencil with Optimized Dataflow Architecture☆18Feb 27, 2024Updated 2 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆86Nov 26, 2025Updated 3 months ago
- ☆13Jul 28, 2022Updated 3 years ago
- DATuner Repository☆17Sep 9, 2018Updated 7 years ago
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆18Nov 12, 2025Updated 4 months ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆57Jun 12, 2021Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago