I-Doctor / gnn-acceleration-framework-with-FPGALinks
including compiler to encode DGL GNN model to instructions, runtime software to transfer data and control the accelerator, and hardware verilog code that can be implemented on FPGA
☆12Updated last year
Alternatives and similar repositories for gnn-acceleration-framework-with-FPGA
Users that are interested in gnn-acceleration-framework-with-FPGA are comparing it to the libraries listed below
Sorting:
- An end-to-end GCN inference accelerator written in HLS☆18Updated 3 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆20Updated 3 years ago
- ☆16Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆14Updated last year
- [FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heteroge…☆17Updated 4 years ago
- NeuraChip Accelerator Simulator☆14Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- [HPCA 2022] GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design☆36Updated 3 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆17Updated 11 months ago
- ☆10Updated 2 years ago
- ☆33Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- ☆17Updated 4 years ago
- STONNE Simulator integrated into SST Simulator☆21Updated last year
- GNNear: Accelerating Full-Batch Training of Graph NeuralNetworks with Near-Memory Processing☆13Updated 3 years ago
- ☆25Updated last year
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆18Updated last year
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 3 years ago
- ☆16Updated 3 years ago
- ☆41Updated last year
- ☆13Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆38Updated 2 years ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 7 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆21Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago